T7115AMCD LSI, T7115AMCD Datasheet - Page 31

• Manufacturer Part Number: T7115AMCD
• Manufacturer: LSI

Specifications of T7115AMCD

• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Data Sheet
April 1997
Lucent Technologies Inc.
Functional Description
Table 8. Register R1—Transmitter Control Register
* Do not set TABT and TFC to 1 at the same time.
Register
R1—B7
R1
R1
R1
TFC
(0)
B(0—5)
B6*
B7*
Bit
R1—B6
TABT
(0)
TIL0—TIL5 Transmitter Interrupt Level. These bits specify the minimum number of
Symbol
TABT
TFC
R1—B5
(continued)
TIL5
(0)
empty positions in the transmit FIFO which triggers a transmitter-empty (TE)
interrupt. Encoding is in binary, bit 0 is the LSB. A code of 001010, for exam-
ple, means an interrupt is generated when the transmit FIFO has ten or more
empty locations. The code 000000 is a special case and means a TE inter-
rupt is generated only when the transmit FIFO is actually empty. The exact
number of empty locations can be obtained by reading the transmitter status
register (R2).
Transmit Abort. Setting this bit to 1 instructs the internal HDLC transmitter
to abort the frame at the last user data byte waiting for transmission. When
the transmitter reads the byte tagged with TABT, it sends the abort sequence
(01111111) in place of that byte. A full byte is guaranteed to be transmitted.
The last value written to TABT is available for reading. Clearing this bit to 0
has no effect on a previously written TABT, i.e., once set for a specific data
byte, TABT cannot be cleared by writing to register 1.
Transmit Frame Complete. Setting this bit to 1 instructs the internal HDLC
transmitter to close the frame normally after the last user data byte written to
the transmit FIFO. The CRC sequence and a closing flag are appended. This
bit should be set within eight CLKX periods of writing the last data byte of the
frame to the queue. When the FIFO is empty, writing two data bytes to the
FIFO before setting TFC provides a minimum of eight CLKX periods to write
TFC. The last value written to TFC is available for reading. Clearing this bit to
0 has no effect on a previously written TFC, i.e., once set for a specific data
byte, TFC cannot be cleared by writing to R1. TFC does not need to be writ-
ten to 0 to begin a new frame.
R1—B4
TIL4
(0)
R1—B3
TIL3
T7121 HDLC Interface for ISDN (HIFI-64)
(0)
Name/Function
R1—B2
TIL2
(0)
R1—B1
TIL1
(0)
R1—B0
TIL0
(0)
31