T7115AMCD LSI, T7115AMCD Datasheet - Page 46

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T7115AMCD

Manufacturer Part Number
T7115AMCD
Description
Manufacturer
LSI
Datasheet

Specifications of T7115AMCD

Package Type
PLCC
Lead Free Status / Rohs Status
Not Compliant
T7121 HDLC Interface for ISDN (HIFI-64)
Clock Characteristics
System Clock Input (CLK): 0 MHz—12 MHz.
Transmit Data Clock (CLKX): no minimum frequency*, <CLK/2 maximum frequency to 4.096 MHz.
Receive Data Clock (CLKR): no minimum frequency*, <CLK/2 maximum frequency to 4.096 MHz.
* 8.192 MHz in CMS mode (R8—B6 = 1).
Timing Characteristics
TDM Frame Timing Diagrams
The timing of the transmission or reception of the first bit relative to the frame-sync pulse depends on the configu-
ration of 3 bits: FE (R0—B5), CLKXI (R9—B4), CLKRI (R9—B0). The timing diagrams below illustrate different
configurations of FE, CLKXI, and CLKRI.
46
CLKX/CLKR
(CLKXI = 0)
(CLKRI = 0)
(FE = 0)
DRA/B
DXA/B
TSCA
FS
FRAME SYNC SAMPLED ON THIS EDGE OF CLKX/CLKR
FIRST BIT TRANSMITTED
Figure 12. FE = 0, CLKXI = 0, CLKRI = 0
0
0
1
FIRST BIT SAMPLED
1
2
2
3
3
4
4
5
5
6
3-STATE
DON'T CARE
6
Lucent Technologies Inc.
7
7
Data Sheet
April 1997
5-5038

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