NAND01GR3B2CZA6E Micron Technology Inc, NAND01GR3B2CZA6E Datasheet - Page 30

• Manufacturer Part Number: NAND01GR3B2CZA6E
• Manufacturer: Micron Technology Inc

Specifications of NAND01GR3B2CZA6E

• Cell Type: NAND
• Density: 1Gb
• Access Time (max): 25us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 8b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: VFBGA
• Program/erase Volt (typ): 1.7 to 1.95V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.95V
• Word Size: 8b
• Number Of Words: 128M
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 63
• Lead Free Status / Rohs Status: Compliant

Device operations
Figure 14. Page copy back program with random data input
6.5
Figure 15. Block erase operation
30/67
RB
I/O
Read
Code
RB
I/O
00h
Block erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the
addressed block to ‘1’. All previous data in the block is lost.
An erase operation consists of three steps (refer to
1.
2.
3.
The operation is initiated on the rising edge of write Enable, W, after the Confirm command
is issued. The P/E/R controller handles block erase and implements the verify process.
During the block erase operation, only the Read Status Register and Reset commands will
be accepted, all other commands will be ignored.
Once the program operation has completed the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High. If the operation completed successfully, the write status bit
SR0 is ‘0’, otherwise it is set to ‘1’.
Block Erase
Setup Code
Add Inputs
One bus cycle is required to setup the Block Erase command. Only addresses A18-
A27 (x8) or A17-A26 (x16) are used, the other address inputs are ignored
Two bus cycles are then required to load the address of the block to be erased. Refer to
Table 8
One bus cycle is required to issue the Block Erase Confirm command to start the P/E/R
controller.
Source
60h
(Read Busy time)
tBLBH1
and
35h
Table 9
Busy
Block Address
Copy Back
Inputs
85h
Code
for the block addresses of each device
Add Inputs
Target
Confirm
Code
D0h
Data
Unlimited number of repetitions
85h
(Erase Busy time)
Figure
tBLBH3
Busy
Add Inputs
2 Cycle
15):
(Program Busy time)
Data
Read Status Register
tBLBH2
70h
10h
Busy
NAND01G-B2C
SR0
70h
ai07593
SR0
ai11001