TSI148-133IL IDT, Integrated Device Technology Inc, TSI148-133IL Datasheet - Page 114

• Manufacturer Part Number: TSI148-133IL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133IL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 800-1905

4. DMA Interface > Direction of Data Movement
4.5.6
4.5.6.1
4.5.6.2
4.5.6.3
114
DMA Transaction Termination
Tsi148 DMA activity can be terminated through either a transfer completion, commanded
stop, commanded abort, or a detected error abort.
Transfer Completion
In most cases, a Direct mode transfer or a Linked-list mode transaction finishes without
intervention or error. In Direct mode operation, the end of the transfer is considered
completion. In Linked-List mode operation, the end of the last transfer of a command is
considered completion. When the transaction is complete, the DMA controller returns a done
status to the DMA Status (DSTA) register (see
enabled, interrupts the processor.
Commanded Stop
The commanded stop termination can be used during Linked-list transactions. Software is
used to set the Commanded Stop bit (PAU) in the DMA Control register (see
on page
When the DMA controller reaches a transfer boundary (that is, ready to fetch the next
descriptor), it stops all DMA activity. If there are more Linked-list commands to be
performed, the DMA controller returns a paused status to the DSTA register and, optionally,
interrupts the processor. If the last command has completed, then the DMA controller returns
a done status to the DSTA register (see
Once the transaction has been stopped, the linked list transaction can be started again at any
time. The DMA controller starts the transaction where it left off. The first descriptor fetch
occurs from the address that was placed within the DMA Next Link Address (DNLA) register
during the previously completed transfer (see
Commanded Abort
The commanded abort termination can occur on either Direct mode or Linked-list mode.
Software is used to set the Commanded Abort bit in the DMA Control (CTL) register (see
Section 10.4.76 on page
When the Commanded Abort bit is set, the DMA controller aborts all DMA activity. This is
considered a non-recoverable termination, and it takes affect immediately after the bit has
been set. If the commanded abort took affect before all commands were completed, then the
DMA controller returns an abort status to the DSTA register and, optionally, interrupts the
processor. If all commands completed before the commanded abort took affect, then the
controller returns a done status to the DMA Status (DSTA) register (see
page
332).
327). This bit can be set at any time during a DMA transaction.
327). This bit can be set at any time during a transaction.
Section 10.4.77 on page
Section 10.4.90 on page
Section 10.4.77 on page
Tsi148 PCI/X-to-VME Bus Bridge User Manual
332).
353).
332) and, when
Section 10.4.77 on
80A3020_MA001_13
Section 10.4.76