TSI148-133IL IDT, Integrated Device Technology Inc, TSI148-133IL Datasheet - Page 260

• Manufacturer Part Number: TSI148-133IL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133IL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 800-1905

10. Registers > Register Map
260
SRTT (Split Response Time-out Test): When this bit is set, the split response time-out time
is reduced for test purposes. Only single beat transfers are supported. When this bit is cleared,
the split response time-out time is controlled by the SRTO field. This bit is provided for test
purposes.
CCTM (Configuration Cycle Test Mode): When this bit is set, any VME to PCI/X cycle
that uses inbound map decoder number 7 generates PCI/X configuration read and write
cycles. Only single beat transfers are supported. When this bit is cleared, inbound map
decoder 7 behaves normally. This bit is provided for test purposes.
DRQ (Disregard REQ64_ Qualification): This bit must be cleared to comply with the PCI
Local Bus Specification (Revision 2.2).
DTTT (Delayed Transaction Time-out Test): When this bit is set, a delayed transaction
times-out after 160 PCI/X bus clocks. When this bit is cleared, a delayed transaction times-out
after 2^15 clocks. This bit reduces the time-out count for test purposes.
MRCT (Maximum Retry Count Test): When this bit is set and the MRC bit is set, the
PCI/X Master retries 16 times before indicating an error. When this bit is cleared and the
MRC bit is set, the PCI/X Master retries 2^24 times before indicating an error. This bit
reduces the retry count for test purposes.
MRC (Maximum Retry Count): When this bit is set, the PCI/X Master counts the number
of sequential cycles that are retried. If the count is exceeded, thePCI/X Master aborts the
transfer. When this bit is cleared, there is no limit to the number of retry attempts.
SBH (Stop on Byte Holes): When this bit is set and the PCI/X bus is configured for
conventional mode, the PCI Target issues a stop command when a transfer has non contiguous
byte enables. When this bit is clear, thePCI Target issues multiple linkage commands to
handle transfers with non contiguous byte enables. This bit is provided for diagnostic
purposes.
SRTE (Split Response Time-out Error): This bit is set when a split response time-out error
occurs. This bit is cleared by writing a one to this bit.
DTTE (Delayed Transaction Time-out Error): This bit is set when a delayed transaction
time-out error occurs. This bit is cleared by writing a one to this bit.
MRCE (Maximum Retry Count Error): This bit is set when the MRC bit is set and the
maximum number of retries is exceeded. This bit is cleared by writing a one to this bit.
This bit should be cleared to comply with the PCI Local Bus Specification
(Revision 2.2).
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13