TSI148-133IL IDT, Integrated Device Technology Inc, TSI148-133IL Datasheet - Page 36

• Manufacturer Part Number: TSI148-133IL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133IL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 800-1905

1. Functional Overview > PCI/X Interface
1.3.1.3
1.3.1.4
1.3.2
1.3.2.1
36
PCI-X Target
Read transactions from the PCI-X bus are always processed as split transactions. The PCI-X
Target has a 4 Kbyte read buffer used for storing prefetched data. The requesting external
PCI-X master is issued a split response from the Tsi148 PCI-X Target. The PCI-X Target
supports up to six split read transactions.
When the read data has been retrieved from the VMEbus and sent to the PCI-X Target’s
read buffer, Tsi148 issues a split completion on the PCI-X bus and transfers the data from
the PCI-X Target’s read data buffer to the original master .
During write transactions, the PCI-X Target posts write data in its write buffer. The write
buffer consists of a 40 entry command queue and a 4 Kbyte data queue. Tsi148 issues the
initiating PCI bus master immediate acknowledgement upon the write completing. Once the
posted write completes on PCI-X, Tsi148 obtains the VMEbus and writes the data to the
VMEbus resource independent of the initiating PCI-X master.
Features Not Supported
The following features are not supported by the Tsi148 PCI-X Target:
PCI/X Master
Tsi148 requests PCI/X ownership when the PCI/X Master is internally requested by Linkage
Module to service the VME Slave or the DMA controllers.
The PCI/X Master has a 4 Kbyte read buffer and 4 Kbyte write buffer.
Features Not Supported
The following features are not supported in Tsi148:
— Message signalled interrupts
— No response to PCI-X I/O transfers
— PCI/X LOCK_ signal
— Message signalled interrupts
— PCI/X LOCK_ signal
Prefetching is based on the byte count received by the Tsi148 PCI-X Target.
The size of the read buffer is dependent on what PCI/X mode (PCI or PCI-X) is
used in the system (see
Section 1.3.1.1 on page
Tsi148 PCI/X-to-VME Bus Bridge User Manual
35).
80A3020_MA001_13