TSI148-133IL IDT, Integrated Device Technology Inc, TSI148-133IL Datasheet - Page 94
![IC PCI-VME BRIDGE 456PBGA](/photos/6/93/69324/tsi148-133il_sml.jpg)
TSI148-133IL
Manufacturer Part Number
TSI148-133IL
Description
IC PCI-VME BRIDGE 456PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Series
Tsi148&Trade;r
Datasheets
1.TSI148-133CL.pdf
(391 pages)
2.TSI148-133CL.pdf
(2 pages)
3.TSI148-133CL.pdf
(12 pages)
Specifications of TSI148-133IL
Applications
PCI-to-VME Bridge
Interface
PCI
Voltage - Supply
3.3V
Package / Case
456-PBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
800-1905
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3. PCI/X Interface > PCI-X Mode
3.3.3.2
94
PCI-X Target Exception Handling
The error diagnostic registers are updated when the PCI-X Target detects an address parity
error, a data parity error has occurred, or a unexpected split completion is received.
When the PCI-X Target detects a address parity error the following steps are taken:
•
•
When the PCI-X Target detects a data parity error the following steps are taken:
•
•
•
When the PCI-X Target receives an unexpected split completion the following steps are
taken:
•
Generate SERR (if enabled)
Log status information
Generate PERR (if enabled)
Log status information and update PCI-X bus exception registers (see
page
Optional: step generate interrupt
The split completion is discarded and the Split Completion Discarded (SCD) bit is set in
the Error Diagnostic PCI Attribute register (see
272)
If the PCI-X Target detects the assertion of the SERR_ signal, no action is taken.
Section 10.4.43 on page
Tsi148 PCI/X-to-VME Bus Bridge User Manual
Section 10.4.43 on
80A3020_MA001_13
272).
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