DS33X81+ Maxim Integrated Products, DS33X81+ Datasheet - Page 143

• Manufacturer Part Number: DS33X81+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X81+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
004h:
Default
Bit 3: Interrupt Mode (INTM) When this bit is set to 1, the inactive state of the INT pin will be high-impedance.
When this bit is equal to 0, the inactive state of the INT pin will be a driven logic high.
Bit 2: Encap/Decap Loopback (ENDEL) When this bit is set to 1, the WAN-side output data from Encapsulator #1
is looped back to the WAN input of Decapsulator #1.
Bit 0: Global Reset (RST) When this bit is set, all of the internal data path, status, and control registers (except the
RST bit), on all ports, will be reset to the default state. This bit must remain set to 1 for a minimum of 100ns to
initiate the reset operation. The bit should be cleared to 0 for normal operation to resume. Note that setting this bit
does not tri-state output pins. When using a revision A1 (GL.IDR.REVn=000) device in SPI mode, the individual
block reset bits or the hardware reset pin should be used instead of this bit.
Rev: 063008
005h:
Default
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Bit 15
Bit 7
0
0
-
-
Bit 14
Bit 6
0
0
-
-
GL.CR2
Global Control Register 2
004h
Bit 13
Bit 5
0
0
-
-
Bit 12
Bit 4
0
0
-
-
Bit 11
INTM
Bit 3
0
0
-
ENDEL
Bit 10
Bit 2
0
0
-
Bit 9
Bit 1
0
0
-
-
143 of 375
Bit 8
Bit 0
RST
0
0
-