DS33X81+ Maxim Integrated Products, DS33X81+ Datasheet - Page 150

• Manufacturer Part Number: DS33X81+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X81+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

02Fh:
Default
031h:
Default
Register Name:
Register Description:
Register Address:
02Eh:
Default
Bit 3: LAN Extraction Available Interrupt Enable (LANEAIE) This bit enables LANEAL to cause an interrupt.
Bit 2: LAN Insertion Empty Interrupt Enable (LANIEIE) This bit enables an interrupt if the LANIEL bit is set.
Bit 1: WAN Extraction Available Interrupt Enable (WANEAIE) This bit enables WANEAL to cause an interrupt.
Bit 0: WAN Insertion Empty Interrupt Enable (WANIEIE) This bit enables an interrupt if the WANIEL bit is set.
Register Name:
Register Description:
Register Address:
030h:
Default
Bit 9: Read Byte (RD_DN) A zero-to-one transition is required after the last byte of the frame has been read from
the MFAWR Register. This signals the associated FIFO (WAN Extract or LAN Extract) to reset its pointers.
Bit 8: Write Byte (WR_DN) A zero-to-one transition is required after the last byte of the frame has been written to
MFAWR Register. This transition signals that the frame is ready to be transferred.
Bits 0-7: Packet Write Byte (WPKT[7:0]) If an Insertion FIFO is selected, this register inserts a byte of frame data
into the FIFO selected by MCR2. The beginning of the frame to be transmitted is written first. Each write
automatically increments the FIFO pointer. If an Extraction FIFO is selected, this register reports a byte of frame
data from the FIFO selected by MCR2. The beginning of the frame to be transmitted is read first. Each read
automatically increments the FIFO pointer.
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
WPKT7
Bit 15
Bit 15
Bit 7
Bit 7
0
0
0
0
-
-
-
WPKT6
Bit 14
Bit 14
Bit 6
Bit 6
0
0
0
0
-
-
-
GL.MSIER3
Microport Status Interrupt Enable Register 3
02Eh
GL.MFAWR
Microport FIFO Access Write Register
030h
WPKT5
Bit 13
Bit 13
Bit 5
Bit 5
0
0
0
0
-
-
-
WPKT4
Bit 12
Bit 12
Bit 4
Bit 4
0
0
0
0
-
-
-
LANEAIE
WPKT3
Bit 11
Bit 11
Bit 3
Bit 3
0
0
0
0
-
-
LANIEIE
WPKT2
Bit 10
Bit 10
Bit 2
Bit 2
0
0
0
0
-
-
WANEAIE
RD_DN
WPKT1
Bit 9
Bit 1
Bit 9
Bit 1
0
0
0
0
-
WANIEIE
WR_DN
150 of 375
WPKT0
Bit 8
Bit 0
Bit 8
Bit 0
0
0
0
0
-