DS33X81+ Maxim Integrated Products, DS33X81+ Datasheet - Page 52

• Manufacturer Part Number: DS33X81+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X81+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.11 Serial (WAN)
The Serial Interfaces support time-division multiplexed, serial data I/O up to 52Mbps. The Serial Interface receives
and transmits encapsulated Ethernet frames, and consists of a physical serial port with a GFP/X.86/HDLC/cHDLC
engine. Each physical interface consists of a data pin, clock pin, and a synchronization pin in both the transmit and
receive directions. The Serial Interface can operate with a gapped clock, and can be connected to a framer,
electrical LIU, optical transceiver, or T/E-Carrier transceiver for WAN transmission. The Serial Interface can be
seamlessly connected to the Maxim T1/E1/J1 Framers, Line Interface Units (LIUs), and Single-Chip Transceivers
(SCTs). The interface can also be seamlessly connected to the Maxim T3/E3/STS-1 Framers, LIUs, and SCTs to
provide T3, E3, and STS1 connectivity.
Receive features:
Transmit features:
8.11.1 Voice Support (DS33W11 and DW33W41 Only)
Voice demuxing is done on Frame Sync boundaries, with a programmable number of octets (with a maximum of
16) to be demuxed to the Voice FIFO. These are the octets immediately following the Frame Sync boundary. Voice
octets are read from Voice FIFO one frame later after written to FIFO.
Voice Muxing occurs on Frame Sync boundaries and a programmable number of octets(with a maximum of 16) are
read from the Voice FIFO. These octets will appear on TDATA immediately following the TMSYNC/TSYNC signal.
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
User configurable receive serial ports (up to 16)
User configurable receive voice port(s) (DS33W41/DS33W11 only)
Programmable clock inversion
Serial data is byte-aligned with reference to Receive Frame Sync (MSB follows Frame Sync)
Demuxes Voice traffic from T1/E1/xDSL (maximum of 16 DS0s per port) and output on voice port
(DS33W41/DS33W11 only)
Buffers demuxed voice traffic and realign with RVSYNC and RVCLK (DS33W41/DS33W11 only)
Reports Loss of RCLKn
Capability of RDATA to TDATA loopback
Reports FIFO underflow/overflow
Data is byte-aligned to TMSYNC/TSYNC (MSB follows TMSYNC/TSYNC)
TMSYNC/TSYNC is an input that may be lined up with the framing overhead of the T1/E1/T3/E3 frame or
programmable to be expected three cycles early.
User configurable transmit ports (up to 16)
User configurable transmit voice port(s) (DS33W41/DS33W11 only)
Programmable clock inversion
Muxes Voice traffic to T1/E1/xDSL (DS33W41/DS33W11 only, ports 1-4)
Buffers voice traffic(maximum 16 DS0s per port) to mux in with frame data and retime to TMCLK/TCLK and
TMSYNC/TSYNC (DS33W41/DS33W11 only)
Reports Loss of TCLK
Capable of TDATA to RDATA loopback (replaces RCLK with TMCLK/TCLK)
52 of 375