DS33X81+ Maxim Integrated Products, DS33X81+ Datasheet - Page 87

• Manufacturer Part Number: DS33X81+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X81+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
In HDLC/cHDLC/LAPS(X.86) mode, the inter-frame fill is selectable per WAN group with PP.EMCR.EIIS. If packet
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processing is disabled, inter-frame padding is not performed. The frame scrambler is a x
+ 1 scrambler that
scrambles the entire frame data stream. Frame scrambling is selectable per WAN group with PP.EMCR.ECFCRD.
To optimize WAN bandwidth in point-to-point applications, the Ethernet header information may be removed from
the datagram prior to encapsulation. The Encapsulator can be configured to remove either 14 or 18 bytes from
each incoming frame using the PP.EMCR.ERE[1:0] bits. Byte removal starts with the DA field. Removing 14 bytes
will remove the DA, SA, and Length/Type fields. Removing 18 bytes will remove the DA, SA, Length/Type, and
VLAN Tag fields. Once all packet processing has been completed, the serial data stream is forwarded.
Note that some devices in the product family have less than four encapsulators. The DS33X11 contains only
Encapsulator #1. The DS33W41 and DS33X42 contain only encapsulators #1 and #3.
8.20.2 Receive Packet Processor (Decapsulator)
The Receive Packet Processor accepts data from the Receive Serial Interface performs frame descrambling, frame
delineation, inter-frame fill filtering, frame abort detection, destuffing, frame size checking, FCS error monitoring,
FCS byte extraction, and bit reordering. Frame delineation determines the frame boundary by identifying a frame
start or end flag. Receive packet processing can be disabled. Disabling packet processing disables frame
delineation, inter-frame fill filtering, frame abort detection, destuffing, frame size checking, FCS error monitoring,
and FCS byte extraction. Only frame descrambling and bit reordering are not disabled. The frame descrambler is a
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self-synchronizing x
+ 1 descrambler.
Inter-frame fill filtering removes the inter-frame fill between frames. When a frame end flag is detected, all data is
discarded until a frame start flag is detected. The inter-frame fill can be flags or all 1s. The number of 1s between
flags does not need to be an integer number of bytes, and if at least seven 1s are detected in the first 16 bits after a
flag, all data after the flag is discarded until a start flag is detected.
Frame abort detection searches for a frame abort sequence between the frame start flag and a frame end flag, if an
abort sequence is detected, the frame is marked with an abort indication, the aborted frame count is incremented,
and all subsequent data is discarded until a valid frame start flag is detected.
Destuffing removes the extra data inserted to prevent data from mimicking a HDLC/cHDLC/X.86 flag or an abort
sequence. A start flag is detected, destuffing is performed until an end flag is detected. The start and end flags are
discarded. In bit synchronous mode, bit destuffing is performed. Bit destuffing consists of discarding any '0' that
directly follows five contiguous 1s. After destuffing is completed, the serial bit stream is forwarded.
Frame size validation checks each frame for a programmable maximum size. As the frame data comes in, the total
number of bytes is counted. If the frame length is below the minimum size limit, the frame is marked with an
aborted indication, and the frame size violation count is incremented. If the frame length is above the maximum
size limit, the frame is marked with an aborted indication, the frame size violation count is incremented, and all
frame data is discarded until a frame start is received. The minimum and maximum lengths include the FCS bytes,
and are determined after destuffing has occurred.
FCS error monitoring checks the FCS and aborts errored frames. If an FCS error is detected, the FCS errored
frame count is incremented and the frame is marked with an aborted indication. If an FCS error is not detected, the
receive frame count is incremented. The FCS type (16-bit or 32-bit) is programmable.
FCS byte extraction discards the FCS bytes. If FCS extraction is enabled, the FCS bytes are extracted from the
frame and discarded. If FCS extraction is disabled, the FCS bytes are stored in the receive FIFO with the frame.
Bit reordering changes the bit order of each byte. Normally, the first bit of each byte in the received data stream is
assumed to be the MSB. If bit reordering is enabled, the first bit of each byte in is assumed to be the LSB. Once all
of the packet processing has been completed, the data stream is passed to the WAN Queues. Bit reordering is
configured using the PP.DMCR.RBRE bit. Note that bit reordering is not available in the A1 device revision
(GL.IDR.REVn=000).
The Decapsulator collects 2 statistics; the number of good frames and number of errored frames due any errors.
These statistics are latched bit counters and are cleared when read by the user.
The Decapsulator must be configured to remove the 4-byte encapsulation line header information if it is present.
The 4-byte removal function is selected using the PP.DMCR.DR1E control bit. When enabled, 4 bytes are removed
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