DS33X81+ Maxim Integrated Products, DS33X81+ Datasheet - Page 236

• Manufacturer Part Number: DS33X81+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X81+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.6 Decapsulator Registers
Register Name:
Register Description:
Register Address:
301h:
Default
300h:
Default
Bit 15: Decapsulator GFP CRC Mode (DGCM)
Bit 14: Decapsulator Protocol Selection (DPRTSEL)
Selects between GFP and HDLC based forms of encapsulation. Additionally, when transitioning HDLC between
byte and bit modes of operation, this byte is used to reset the HDLC circuitry. In order to initiate a reset the HDLC
circuitry during bit/byte stuffing mode changes, this bit must be set to zero briefly, then set back to 1.
Bit 13: Decapsulator Frame Check Sequence Append Disable (DFCSAD)– When equal to 0, the incoming
frame’s encapsulation (HDLC/GFP) CRC (FCS) will be validated and removed. When set to 1, the decapsulated
frame will not be expected to contain an encapsulation CRC and no bytes will be removed.
Bit 12: Decapsulator Scrambler Disable (DCFCRD) When set to 1, the X
Bit 11: Decapsulator 16-bit FCS Enable (DFCS16EN) When set to 1 the decapsulated frame must contain a 16-
bit FCS. When equal to zero, a 32-bit FCS is expected. This bit is relevant if DFCSAD is reset.
Bit 9: Decapsulator Bit Byte Synchronous(DBBS) When set to 1, the Decapsulator expects byte-stuffed HDLC.
When equal to zero, the Decapsulator expects bit-stuffed HDLC. When in GFP mode (DPRTSEL = 0), this bit
should be set to 1. After changing this bit, the HDLC circuitry should be reset using the PP.DMCR.DPRTSEL bit.
Bit-stuffed HDLC is not valid for multi-member VCGs (WAN Groups).
Bit 8: Receive Bit Reorder (RBRE) Controls the endian order of HDLC reception. This bit function is not available
in device revision A1 (GL.IDR.REVn=000).
Bit 7: Decapsulator Remove Function 1 Enable (DR1E) When set to 1, 4 bytes are removed immediately after
the cHEC bytes (for GFP) or start of HDLC flag (for HDLC). This bit should be set to 1 for X.86, Cisco HDLC and
GFP transport. This bit should be reset to 0 for HDLC traffic with no headers.
Bit 6: Decapsulator Remove Function 2 Enable (DR2E) When set to 1, 4 bytes are removed after the first
remove function. This function should always be used in conjunction with Decapsulator Remove Function 1.
Bit 5: Decapsulator Remove Function 3 Enable (DR3E) When set to 1, 12 bytes are skipped and then 4 bytes
are removed. The 12 bytes are skipped after either Decapsulator Remove Function 1 and/or Decapsulator Remove
Function 2 have been performed (when enabled). When Decapsulator Remove Functions 1 and 2 are disabled, 12
bytes are skipped from the beginning of the frame.
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
0=GFP Null. Decapsulator does not verify the eHEC value.
1=GFP Linear. Decapsulator verifies the eHEC value and discards failing frames.
0=GFP Based.
1=HDLC Based.
0 = HDLC payload will be received MSB-first. Default operation.
1 = HDLC payload will be received LSB-first.
DGCM
Bit 15
DR1E
Bit 7
0
0
DPRTSEL
Bit 14
DR2E
Bit 6
0
0
PP.DMCR
Decapsulator Master Control Register
300h (+ 040h x (n-1), WAN Group Decapsulator n=1 to 4)
DFCSAD
DR3E
Bit 13
Bit 5
0
0
DCFCRD
DAE1
Bit 12
Bit 4
0
0
DFCS16EN
DAE0
Bit 3
Bit 11
0
0
43
+1 descrambler is turned off.
DGSC
Bit 2
Bit 10
0
0
-
DHRAE
DBBS
Bit 9
Bit 1
0
0
DHCBO
236 of 375
RBRE
Bit 8
Bit 0
0
0