DS33X81+ Maxim Integrated Products, DS33X81+ Datasheet - Page 2

• Manufacturer Part Number: DS33X81+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X81+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Rev: 063008
_________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
5.1
5.2
5.3
5.4
5.5
5.6
7.1
8.1
8.2
8.3
2.3.1
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.7.6
2.7.7
2.7.8
2.7.9
2.8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.3.1
8.3.2
DETAILED DESCRIPTION .............................................................................................................. 9
FEATURE HIGHLIGHTS................................................................................................................ 10
APPLICABLE EQUIPMENT TYPES..............................................................................................14
ACRONYMS & GLOSSARY ..........................................................................................................17
DESIGNING WITH THE DS33X162 FAMILY OF DEVICES..........................................................18
BLOCK DIAGRAMS ...................................................................................................................... 20
PIN DESCRIPTIONS ...................................................................................................................... 21
FUNCTIONAL DESCRIPTION .......................................................................................................34
G
VCAT/LCAS L
HDLC........................................................................................................................................... 10
GFP-F.......................................................................................................................................... 11
X.86 S
DDR SDRAM I
MAC I
S
M
I
D
A
C
B
S
P
P
SPI S
C
DENTIFICATION OF
ERIAL
NCILLARY
OARD
OFTWARE
IN
ARALLEL
EVICE
IRCUIT
LOCK
ENERAL
ICROPROCESSOR
S
T
S
EST AND
LAVE
PECIFICATIONS
F
cHDLC.................................................................................................................................................. 10
Ethernet Bridging for 10/100 ................................................................................................................ 12
Ethernet Traffic Classification .............................................................................................................. 12
Ethernet Bandwidth Policing ................................................................................................................ 12
Ethernet Traffic Scheduling.................................................................................................................. 12
Connection Endpoints .......................................................................................................................... 12
Virtual Connection................................................................................................................................ 12
Connection and Aggregation ............................................................................................................... 12
Ethernet Control Frame Processing..................................................................................................... 12
Q-in-Q .................................................................................................................................................. 12
Voice Ports........................................................................................................................................... 13
Read-Write/Data Strobe Modes........................................................................................................... 35
Clear on Read ...................................................................................................................................... 35
Interrupt and Pin Modes....................................................................................................................... 35
Multiplexed Bus Operation................................................................................................................... 35
Serial Interface Clock Modes ............................................................................................................... 39
Ethernet Interface Clock Modes........................................................................................................... 39
UNCTIONAL
ERIAL
NTERFACES
UPPORT
S
P
L
S
D
AYOUT
TRUCTURE
ORTS
S
ELECTION
...................................................................................................................................... 10
ESIGN
P
ERIAL
D
D
ROCESSOR
P
D
EVICE
EVELOPMENT
ROCESSOR
IAGNOSTICS
INK
..............................................................................................................................13
NTERFACE
.............................................................................................................................11
.............................................................................................................................19
............................................................................................................................19
P
D
.........................................................................................................................11
ERIPHERAL
A
ESCRIPTION
C
A
S
I
.......................................................................................................................18
.......................................................................................................................37
NTERFACE
GGREGATION
OMPLIANCE
PPLICATION
ELECTION
I
NTERFACE
I
NTERFACE
.............................................................................................................11
.............................................................................................................13
............................................................................................................19
I
NTERFACE
......................................................................................................13
......................................................................................................19
......................................................................................................21
....................................................................................................13
R
(I
EQUIREMENTS
................................................................................................35
NVERSE
.............................................................................................36
(SPI) F
M
ULTIPLEXING
EATURES
..........................................................................18
) ..........................................................10
............................................................13
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