DS33X81+ Maxim Integrated Products, DS33X81+ Datasheet - Page 39

• Manufacturer Part Number: DS33X81+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X81+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.3.1
Serial Interface timing is determined by the line clocks. Both the transmit and receive clocks (TCLK and RCLK) are
inputs, and can be gapped.
8.3.2
The Ethernet interfaces can be configured for MII, RMII, or GMII operation with the GL.CR1.P1SPD,
GL.CR1.P2SPD, SU.MACCR.GMIIMIIS bits and the RMII_SEL input pin. See Table 8-1 for details of the clock
requirements for the various Ethernet Interface configurations.
8.4
The external RST pin and the reset bit GL.CR2.RST generate global reset signals. A global reset signal resets the
status and control registers on the chip (except the GL.CR2.RST bit) to their default values and resets all the other
flops to their reset values. The processor bus output signals are also placed in high-impedance mode when the
RST pin is active (low). The global reset bit (GL.CR2.RST) stays set after a one is written to it, but is reset to zero
when the external RST pin is active or when a zero is written to it. The system clock must be active for the device to
properly execute the reset. Allow 5 milliseconds after initiating a reset condition for the reset operation to complete.
The DS33X162 family of devices contain up to 54 individual software reset bits, depending on the port count of the
device. These functions of the various reset bits are outlined in the table below.
Table 8-2. Software Reset Functions
Bit Location
GL.CR2.RST
SU.BFC.BFTR
SU.LP1C.LP1FR
SU.LP2C.LP2FR
AR.LQ1SA – AR.LQ16SA.LQnPR
AR.WQ1SA – AR.WQ16SA.WQnPR
AR.LIQSA.LIQPR
AR.LEQSA.LEQPR
AR.WIQSA.WIQPR
AR.WEQSA.WEQPR
AR.MQC.ASQPR
PP.DFSCR.DSMR (1-4)
PP.DFSCR.DEPRE (1-4)
VCAT.RCR4.RFRST (1-16)
LI.TVPCR.TVFRST
LI.RCR1.RFRST (1-16)
LI.RVPCR.RVRST
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Resets and Low-Power Modes
Serial Interface Clock Modes
Ethernet Interface Clock Modes
Function
Global Device Reset.
Resets each of the 4096 Bridge Filter Table entries.
LAN port FIFO Reset
LAN port FIFO Reset
LAN Queue Pointer Reset
WAN Queue Pointer Reset
LAN Insert Queue Pointer Reset
LAN Extract Queue Pointer Reset
WAN Insert Queue Pointer Reset
WAN Extract Queue Pointer Reset
LAN Queue, WAN Queue, LAN Insert Queue, LAN
Extract Queue, WAN Insert Queue, and WAN Extract
Queue Reset.
Decapsulator Reset
Pointer Reset Enable
VCAT Receive FIFO Reset/Power-Down.
Transmit Voice FIFO Reset/Power-Down.
Receive FIFO Reset/Power-Down.
Receive Voice FIFO Reset/Power-Down.
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