DS33X81+ Maxim Integrated Products, DS33X81+ Datasheet - Page 8

• Manufacturer Part Number: DS33X81+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X81+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
List of Tables
Table 1-1. Product Selection Matrix............................................................................................................................. 9
Table 7-1. Detailed Pin Descriptions ......................................................................................................................... 21
Table 8-1. Clocking Options for the Ethernet Interface ............................................................................................. 37
Table 8-2. Software Reset Functions ........................................................................................................................ 39
Table 8-3. Block Enable Functions ............................................................................................................................ 40
Table 8-4. Forwarding Modes Supported by Device ................................................................................................. 49
Table 8-5. Maximum Number of T3/E3 Lines Per Encapsulator (DS33X162 and DS33X82 Only) .......................... 51
Table 8-6. VCAT/LCAS Control Frame for T1/E1...................................................................................................... 53
Table 8-7. VCAT/LCAS Control Frame for T3/E3...................................................................................................... 54
Table 8-8. Configuration Recommendations for Maximum Frame Length................................................................ 61
Table 8-9. Selection of MAC Interface Modes for Port 1 ........................................................................................... 61
Table 8-10. Selection of MAC Interface Modes for Port 2......................................................................................... 61
Table 8-11. MII Mode Options ................................................................................................................................... 64
Table 8-12. Example Priority Table Configuration for DSCP .................................................................................... 72
Table 8-13. Example Priority Table Configuration for PCP ....................................................................................... 73
Table 8-14. MAC Control Registers........................................................................................................................... 81
Table 8-15. MAC Status Registers ............................................................................................................................ 81
Table 8-16. MAC Counter Registers.......................................................................................................................... 82
Table 8-17. GFP Type/tHEC Field (Payload Header) Definition ............................................................................... 89
Table 8-18. GFP UPI Definitions ............................................................................................................................... 89
Table 8-19. Example GFP Type + tHEC Values ....................................................................................................... 90
Table 8-20. GFP CID/Spare/eHEC (Extension Header) Field Definition................................................................... 92
Table 8-21. Example CID + Spare + eHEC Values................................................................................................... 92
Table 8-22. Credit Threshold Settings with Resulting Bandwidths.......................................................................... 100
Table 10-1. Register Address Map .......................................................................................................................... 105
Table 10-2. Global Register Bit Map........................................................................................................................ 106
Table 10-3. MAC Indirect Register Bit Map ............................................................................................................. 131
Table 10-4. Default GL.IDR Values ......................................................................................................................... 141
Table 10-5. Valid Conditions for MPL > 2048.......................................................................................................... 182
Table 12-1. Recommended DC Operating Conditions ............................................................................................ 339
Table 12-2. DC Electrical Characteristics................................................................................................................ 340
Table 12-3. Thermal Characteristics........................................................................................................................ 341
Table 12-4. Transmit GMII Interface........................................................................................................................ 342
Table 12-5. Receive GMII Interface......................................................................................................................... 343
Table 12-6. Transmit MII Interface........................................................................................................................... 344
Table 12-7. Receive MII Interface............................................................................................................................ 345
Table 12-8. Transmit RMII Interface ........................................................................................................................ 346
Table 12-9. Receive RMII Interface ......................................................................................................................... 347
Table 12-10. MDIO Interface ................................................................................................................................... 348
Table 12-11. Transmit WAN Interface ..................................................................................................................... 349
Table 12-12. Receive WAN Interface ...................................................................................................................... 350
Table 12-13. Transmit Voice Port Interface............................................................................................................. 351
Table 12-14. Receive Voice Port Interface.............................................................................................................. 352
Table 12-15. DDR SDRAM Interface....................................................................................................................... 353
Table 12-16. Parallel Microprocessor Bus............................................................................................................... 355
Table 12-17. Multiplexed Microprocessor Bus ........................................................................................................ 358
Table 12-18. SPI Microprocessor Bus Mode........................................................................................................... 361
Table 12-19. JTAG Interface ................................................................................................................................... 362
Table 13-1. Instruction Codes for IEEE 1149.1 Architecture................................................................................... 367
Table 13-2. ID Code Structure................................................................................................................................. 368
Rev: 063008
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