DS33X81+ Maxim Integrated Products, DS33X81+ Datasheet - Page 277

• Manufacturer Part Number: DS33X81+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X81+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
0004h:
Default
0005h:
Default
0006h:
Default
0007h:
Default
Bit 31: Receive All Frames (RAF) - When set to 1, the receiver forwards all frames to the device, even if they do
not pass the destination address filter. When equal to zero, the receiver only forwards those frames that pass the
destination address filter.
Bit 7: Pass Pause Control Frames (PCF) - When set to 1, the receiver forwards all special multicast PAUSE
control frames to the device. The MAC also decodes the PAUSE control frame and disables the transmitter for the
specified amount of time. When equal to zero, the MAC decodes the PAUSE control frame and disables the
transmitter for the specified amount of time, but does not forward the PAUSE frame to the device.
Bit 5: Disable Broadcast Frames (DBF) - When set to 1, the MAC filters all incoming Broadcast frames. When
equal to zero, all broadcast frames are forwarded to the device.
Bit 4: Pass All Multicast (PAM) - When set to 1, all received multicast frames (1
irrespective of the settings of the Hash filter and Inverse Filtering bits.
Bit 3: Inverse Filtering (INVF) - When set to 1, the programmable DA filter operates in inverse filtering mode. The
result of the filtering operations by the Hash HFUF/HFMF bits is inverted. When equal to zero, filtering is
determined by the HFUF/HFMF bits.
Bit 2: Hash Mode for Unicast Frames (HFUF) - When set to 1, address filtering operates in the imperfect (hash)
address filtering mode for unicast frames, according to the hash table. When equal to zero, perfect address filtering
is performed on unicast frames using the addresses specified in the MAC address filter registers.
Bit 1: Hash Mode for Multicast Frames (HFMF) - When set to 1, address filtering operates in the imperfect (hash)
address filtering mode for multicast frames, according to the hash table. When this bit equals zero, perfect address
filtering is performed on multicast frames using the addresses specified in the MAC address filter registers.
Bit 0: Promiscuous Mode (PM) – When set to 1, all non-control frames are allowed to pass, including broadcast
frames, regardless of destination address.
See Section 8.19.3 for more details on frame-filtering configuration.
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Reserved
Reserved
Bit 31
Bit 23
Bit 15
RAF
Bit 7
PCF
0
0
0
0
Reserved
Reserved
Reserved
Reserve
Bit 30
Bit 22
Bit 14
Bit 6
d
0
0
0
0
SU.MACFFR
MAC Frame Filter Register
0004h (indirect)
Reserved
Reserved
Reserved
Bit 29
Bit 21
Bit 13
Bit 5
DBF
0
0
0
0
Reserved
Reserved
Reserved
Bit 28
Bit 20
Bit 12
PAM
Bit 4
0
0
0
0
Reserved
Reserved
Reserved
Bit 27
Bit 19
Bit 11
INVF
Bit 3
0
0
0
0
Reserved
Reserved
Reserved
Bit 10
HFUF
Bit 26
Bit 18
Bit 2
0
0
0
0
st
bit of DA = “1”) are forwarded,
Reserved
Reserved
Reserved
HFMF
Bit 25
Bit 17
Bit 9
Bit 1
0
0
0
0
Reserved
Reserved
Reserved
277 of 375
Bit 24
Bit 16
Bit 0
Bit 8
PM
0
0
0
0