HD64570F16 Renesas Electronics America, HD64570F16 Datasheet - Page 118

• Manufacturer Part Number: HD64570F16
• Description: IC SCA SRL COMM ADAPTER 88QFP
• Manufacturer: Renesas Electronics America

Specifications of HD64570F16

• Applications: ISDN
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 88-QFP
• Mounting Type: Surface Mount
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5.1.2
The MSCI block diagram is shown in figure 1.2.
The MSCI has 27 internal registers that the user can access. These registers specify the operating
mode and control transmission and reception operations.
Receiver: The following describes the operations of the MSCI receiver, referring to figure 1.13.
The MSCI receiver has one 32-stage FIFO receive buffer, five 8-bit shift registers, and one delay
register. The receiver also has a 6-bit status buffer (FIFO). This buffer retains status information,
such as parity or framing errors, related to the received data. Note that status register 2 (ST2) and
current status registers 0 and 1 (CST0 and CST1) are located at the top of the status buffer (FIFO)
and interface with the internal data bus. For details, see sections 5.2.11, MSCI Status Register 2
Rev. 0, 07/98, page 102 of 453
Byte Synchronous Mode
Bit Synchronous Mode
Programmable parity (odd, even, or no parity)
Detection of parity, overrun, and framing errors
Break transmission and reception
Multiprocessor (MP) bit transmission and reception
Programmable bit rate (input clock frequency
8-bit character length
Mono-sync, bi-sync, and external synchronous modes supported
CRC code generation and check. Initial value (all 0s or 1s) selectable for each of CRC-16
Automatic SYN character transmission, detection, and deletion
CRC code transmission or no-transmission in underrun state program-selectable
SYN character or mark transmission in idle state program-selectable
Detection of CRC, overrun, and underrun errors
8-bit character length
HDLC mode supported
Information (I) field configured in bytes
Automatic zero insertion in transmit data and deletion from receive data
Flag or mark transmission program-selectable in idle state
8- or 16-bit address (A) field selectable; Four address field check modes program-
End-of-message detection
CRC code generation and detection
and CRC-CCITT generator polynomials
selectable
Configuration and Operation
1/1, 1/16, 1/32, or 1/64)