HD64570F16 Renesas Electronics America, HD64570F16 Datasheet - Page 52
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HD64570F16
Manufacturer Part Number
HD64570F16
Description
IC SCA SRL COMM ADAPTER 88QFP
Manufacturer
Renesas Electronics America
Datasheet
1.HD64570F16.pdf
(469 pages)
Specifications of HD64570F16
Applications
ISDN
Interface
Serial
Voltage - Supply
4.75 V ~ 5.25 V
Package / Case
88-QFP
Mounting Type
Surface Mount
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64570F16
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64570F16
Manufacturer:
HITACHI/日立
Quantity:
20 000
Company:
Part Number:
HD64570F16V
Manufacturer:
INFINEON
Quantity:
12 000
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1.7.13
Interrupt Control
SCA interrupts are controlled by three interrupt status registers (ISR0, ISR1, ISR2) containing
flags for 20 interrupt sources, three interrupt enable registers (IER0, IER1, IER2) which can mask
the interrupt source flags individually, and one interrupt control register (ITCR) (figure 1.24).
The interrupt sources are located in corresponding functional modules (MSCI, DMAC, timers).
When an interrupt source that is not masked becomes active, the SCA activates INT to request an
MPU interrupt. When the MPU activates INTA in response, the SCA begins an acknowledge
cycle and outputs an interrupt vector according to register settings.
The interrupt control register (ITCR) selects the interrupt priority order, the type of acknowledge
cycle, and the type of vector output. ITCR bits IAK0 and IAK1 select the non-acknowledge, single
acknowledge, or double acknowledge cycle. Nonacknowledge means that the SCA does not output
an interrupt vector when INTA is activated. Single acknowledge means that the SCA outputs a
vector the first time INTA is activated. Double acknowledge means that the SCA outputs a vector
the second time INTA is activated.
ITCR bit VOS selects whether to output the contents of the interrupt vector register (IVR) or
interrupt modified vector register (IMVR) as the vector. Any value can be set in IVR for
unmodified output as the vector in the acknowledge cycle. The highest two bits of IMVR can be
set to any value, but the lower six bits hold a hardware-generated code representing the interrupt
source. If multiple interrupt sources are active simultaneously, IMVR holds the code of the source
with the highest priority. ITCR bit IPC can switch the relative priority of the MSCI and DMAC.
See figures 1.25 to 1.27 for interrupt logic flow for MSCI, DMAC, and timer modules.
Rev. 0, 07/98, page 36 of 453
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