HD64570F16 Renesas Electronics America, HD64570F16 Datasheet - Page 98

• Manufacturer Part Number: HD64570F16
• Description: IC SCA SRL COMM ADAPTER 88QFP
• Manufacturer: Renesas Electronics America

Specifications of HD64570F16

• Applications: ISDN
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 88-QFP
• Mounting Type: Surface Mount
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 4.1 lists the interrupts in priority order and names of their sources.
Table 4.1
Module
MSCI0
MSCI0
MSCI0
MSCI0
MSCI1
MSCI1
MSCI1
MSCI1
DMAC0
DMAC0
DMAC1
DMAC1
DMAC2
DMAC2
DMAC3
DMAC3
Timer 0
Timer 1
Timer 2
Timer 3
Note: The MSCI and DMAC priorities can be interchanged by setting a bit in the interrupt control
Interrupt requests are generated by status bits set in interrupt status registers 0, 1, and 2 (ISR0,
ISR1, ISR2). If a requested interrupt is enabled by the corresponding bit in interrupt enable
register 0, 1, or 2 (IER0, IER1, IER2), the request is sent to the MPU.
See sections 4.2.4 to 4.2.9 for details of interrupt status registers 0 to 2 and interrupt enable
registers 0 to 2.
Rev. 0, 07/98, page 82 of 453
register (ITCR). For details, see section 4.2.3, Interrupt Control Register, and section 4.2.2,
Interrupt Modified Vector Register.
Interrupt Priority and Interrupt Sources
Interrupt Name
RXRDY0
TXRDY0
RXINT0
TXINT0
RXRDY1
TXRDY1
RXINT1
TXINT1
DMIA0
DMIB0
DMIA1
DMIB1
DMIA2
DMIB2
DMIA3
DMIB3
T0IRQ
T1IRQ
T2IRQ
T3IRQ
Priority
High
Low
Interrupt Source
Receive buffer ready
Transmit buffer ready
Receive status
Transmit status
Receive buffer ready
Transmit buffer ready
Receive status
Transmit status
Error interrupt
Normal end interrupt
Error interrupt
Normal end interrupt
Error interrupt
Normal end interrupt
Error interrupt
Normal end interrupt
Count match
Count match
Count match
Count match
(channel 0)
(channel 0)
(channel 0)
(channel 0)
(channel 1)
(channel 1)
(channel 1)
(channel 1)
(channel 0)
(channel 0)
(channel 1)
(channel 1)
(channel 2)
(channel 2)
(channel 3)
(channel 3)
(channel 0)
(channel 1)
(channel 2)
(channel 3)