HD64570F16 Renesas Electronics America, HD64570F16 Datasheet - Page 232

• Manufacturer Part Number: HD64570F16
• Description: IC SCA SRL COMM ADAPTER 88QFP
• Manufacturer: Renesas Electronics America

Specifications of HD64570F16

• Applications: ISDN
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 88-QFP
• Mounting Type: Surface Mount
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

established within a maximum of four transition points. (For FM type codes (FM0, FM1 and
Manchester), synchronization can be established in one level transition by issuing the enter search
mode command.)
The relationship between the extracted clock and the receive data bit cell depends on the receive
data code type. For NRZ and NRZI codes, the rising edge of the extracted clock pulse is located
at the midpoint of the data bit cell width that is output from the data delay unit. For FM0, FM1,
and Manchester codes, the rising edge of the extracted clock is located at the 1/4 point of the data
bit cell width that is output from the data delay unit. This applies also to operating modes
and
is 8 and 16, respectively.
Phase compensation functions for NRZ codes and FM codes are summarizes in table 5.17.
Table 5.17 Phase Compensation for NRZ Codes and FM Codes
Codes
NRZ
NRZI
FM0
FM1
Manchester
T
Note: An enter search mode command is automatically issued; the ADPLL automatically enters
Rev. 0, 07/98, page 216 of 453
B
: One bit cycle of receive data
32 except that the maximum number of level transition points required for synchronization
search mode and attempts to reestablish synchronization at the next transition point if the
Receive Data Transition Points
Bit boundary to 1/2T
Bit boundary to 1/4T
Others
1/2T
1/4T
Others
1/2T
3/4T
1
B
B
B
B
to 3/4T
to 1/2T
to bit boundary
to bit boundary
2
1-bit width (T )
B
B
3
B
B
B
4
5
Phase Compensation
+1 ADPLL operating clock
+1 ADPLL operating clock (Note)
No phase compensation
+1 ADPLL operating clock (Note)
No phase compensation
1 ADPLL operating clock
1 ADPLL operating clock (Note)
1 ADPLL operating clock (Note)
1 ,
5
2
3
4
: Bit boundaries
:
:
:
1
4
1
2
3
4
T
T
T
B
B
B
16