HD64570F16 Renesas Electronics America, HD64570F16 Datasheet - Page 260
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HD64570F16
Manufacturer Part Number
HD64570F16
Description
IC SCA SRL COMM ADAPTER 88QFP
Manufacturer
Renesas Electronics America
Datasheet
1.HD64570F16.pdf
(469 pages)
Specifications of HD64570F16
Applications
ISDN
Interface
Serial
Voltage - Supply
4.75 V ~ 5.25 V
Package / Case
88-QFP
Mounting Type
Surface Mount
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64570F16
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64570F16
Manufacturer:
HITACHI/日立
Quantity:
20 000
Company:
Part Number:
HD64570F16V
Manufacturer:
INFINEON
Quantity:
12 000
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6.2.3
One set of two 8-bit subregisters, serving as the current descriptor address register (CDA: CDAL,
CDAH), is provided for each of channels 0, 1, 2, and 3 (figure 6.3).
Single-Block Transfer Mode: In single-block transfer mode, these subregisters are not used.
Their contents have no effect on operation.
Chained-Block Transfer Mode: In chained-block transfer mode, these subregisters serve as the
current descriptor address register (CDA: CDAL, CDAH). This register must be initialized to the
low-order 16 bits of the 24-bit starting address of the descriptor that indicates the first buffer to be
written or read. Later, after a DMA transfer is initiated, the initial value is updated to the starting
address of the next descriptor by the DMAC when the buffers are switched. The high-order eight
bits of the descriptor are specified by the chain pointer base (CPB) and are not updated by the
DMAC.
This register can be read even when a DMA is enabled. For reading this register in byte units,
read CDAL first. Values read from CDAH are those it contained when CDAL was read.
This register must be set in DMA initial state.
After reset, the value of this register is undefined.
6.2.4
One set of two 8-bit sub-registers, serving as the error descriptor address register (EDA: EDAL,
EDAH), is provided for each of channels 0, 1, 2, and 3 (figure 6.4).
Single-Block Transfer Mode: In single-block transfer mode, these subregisters are not used.
Their contents have no effect on operation.
Rev. 0, 07/98, page 244 of 453
Current Descriptor Address Register (CDA: CDAL, CDAH)
Error Descriptor Address Register (EDA: EDAL, EDAH)
Single-block transfer
mode
Chained-block
transfer mode
Figure 6.3 Current Descriptor Address Register
15
Not used
CDAH
H
8 7
Not used
CDAL
L
0
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