HD64570F16 Renesas Electronics America, HD64570F16 Datasheet - Page 90

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HD64570F16

Manufacturer Part Number
HD64570F16
Description
IC SCA SRL COMM ADAPTER 88QFP
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HD64570F16

Applications
ISDN
Interface
Serial
Voltage - Supply
4.75 V ~ 5.25 V
Package / Case
88-QFP
Mounting Type
Surface Mount
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Note:
CPU Mode 3: The SCA latches the address on lines A
active low. CS and AS must remain low throughout the bus cycle. After the bus cycle ends, they
must go high (inactive). Figure 3.12 shows the slave mode bus timing sequence in CPU mode 3.
Rev. 0, 07/98, page 74 of 453
Read cycle
When R/W is high, if HDS or LDS is low (active) at the rising clock edge between the T
T
on the falling clock edge in the T
the T
WAIT output active high and lets the data bus float. The read cycle can be extended by
delaying the high transition of HDS or LDS.
Write cycle
When R/W is low, if HDS or LDS is low (active) at the falling clock edge in the T
SCA latches the data on the data bus on the falling clock edge in the T
data in the register specified by the address. HDS or LDS must remain low until the falling
clock edge in the T
then drives the WAIT output active high.
CLK
A to A
AS
CS
HDS, LDS
D to D
(In)
R/W
WAIT
D to D
(Out)
3
0
1
0
states, the SCA outputs the contents of the register specified by the address on the data bus
5
State numbers do not match MPU state numbers.
state. When HDS or LDS goes high (inactive), the cycle ends: the SCA then drives the
15
15
7
T
Figure 3.11 Slave Mode Bus Timing Sequence in CPU Mode 2
1
Read cycle SCA
T
2
6
state. When HDS or LDS goes high (inactive), the cycle ends: the SCA
Register address
T
3
T
4
MPU
4
state. HDS or LDS must remain low until the beginning of
T
5
T
Output data
1
T
Write cycle MPU
2
1
to A
T
Register address
3
7
Data latch point
when CS and AS are both driven
T
4
Input data
SCA
T
5
4
state, and stores the
T
6
3
state, the
2
and

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