HD64570F16 Renesas Electronics America, HD64570F16 Datasheet - Page 251

• Manufacturer Part Number: HD64570F16
• Description: IC SCA SRL COMM ADAPTER 88QFP
• Manufacturer: Renesas Electronics America

Specifications of HD64570F16

• Applications: ISDN
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 88-QFP
• Mounting Type: Surface Mount
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5.7
5.7.1
The MSCI can issue four types of interrupt requests: TXRDY, RXRDY, TXINT, and RXINT.
These interrupts are initiated with the status bits (bits 7, 6, 1, and 0) of status register 0 (ST0) and
are enabled/disabled with the enable bits (bits 7, 6, 1, and 0) of interrupt enable register 0 (IE0).
The TXINT and RXINT interrupts are also assigned with status bits and corresponding enable bits
for each source. The status bit and its enable bit are ANDed for each interrupt source. The
interrupt sources are indicated by the TXINT bit (bit 7) or RXINT bit (bit 6) of ST0, regardless of
the values of the TXINTE bit (bit 7) or RXINTE bit (bit 6) of IE0.
5.7.2
The methods for clearing each interrupt are given below.
TXRDY interrupt
Write data to the transmit buffer until the data byte count in the buffer becomes equal to or
greater than TXF + 1, (TXF is the value specified with TX ready control register 1 (TRC1)), or
disable the transmitter. A channel reset or a TX reset command will also clear this interrupt.
RXRDY interrupt
Read data from the receive buffer until it becomes empty. A channel reset or an RX reset
command will also clear this interrupt.
TXINT interrupt
Write a 1 to each status bit. When the interrupt source is an idle transmitter, write transmit
data to the transmit buffer.
RXINT interrupt
Write a 1 to each status bit. When the interrupt source is a parity/MP or CRC error, read
receive data from the receive buffer. In bit synchronous mode, ST2 bit values are transferred
to the frame status register (FST), and ST2 is reset when the last character to be transferred has
been read from the receive buffer at completion of frame transfer. Table 5.23 shows interrupt
types, sources, and clearing procedures.
Interrupts
Interrupt Types and Sources
Interrupt Clear
Rev. 0, 07/98, page 235 of 453