HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 21

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
ADC1413D_SER
Product data sheet
11.3.3 Duty cycle stabilizer
11.3.4 Clock input divider
11.4.1 Serial output equivalent circuit
11.4 Digital outputs
Single-ended or differential clock inputs can be selected via the SPI (see
single-ended is selected, the input pin (CLKM or CLKP) is selected via control bit
SE_SEL.
If single-ended is implemented without setting bit SE_SEL accordingly, the unused pin
should be connected to ground via a capacitor.
The duty cycle stabilizer can improve the overall performance of the ADC by
compensating the input clock signal duty cycle. When the duty cycle stabilizer is active
(bit DCS_EN = logic 1; see
between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled
(DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and
55 %.
Table 12.
The ADC1413D contains an input clock divider that divides the incoming clock by a factor
of 2 (when bit CLKDIV2_SEL = logic 1; see
deliver a higher clock frequency with better jitter performance, leading to a better SNR
result once acquisition has been performed.
The JESD204A standard specifies that if the receiver and the transmitter are DC-coupled,
both must be fed from the same supply.
The output should be terminated when 100  (typical) is reached at the receiver side.
Bit DCS_EN
0
1
Fig 19. CML output connection to the receiver (DC-coupled)
Duty cycle stabilizer
All information provided in this document is subject to legal disclaimers.
+
Rev. 5 — 9 February 2011
Table
12 mA to 26 mA
50 Ω
20), the circuit can handle signals with duty cycles of
−
VDDD
CMLPA/CLMPB
CMLNA/CLMNB
AGND
Dual 14-bit ADC; serial JESD204A interface
Description
duty cycle stabilizer disable
duty cycle stabilizer enable
Table
20). This feature allows the user to
ADC1413D series
100 Ω
RECEIVER
005aaa082
© NXP B.V. 2011. All rights reserved.
Table
20). If
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