HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 25

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
ADC1413D_SER
Product data sheet
Fig 23. Transfer diagram for two data bytes (3-wire type)
SCLK
SDIO
CS
R/W W1
11.6.2 Channel control
W0
A12 A11 A10
The steps for a data transfer:
The two ADC channels can be configured at the same time or separately. By using the
register “Channel index”, the user can choose which ADC channel receives the next
SPI-instruction. By default the channel A and B receives the same instructions in write
mode. In read mode only A is active.
1. The falling edge on pin CS in combination with a rising edge on pin SCLK determine
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can vary in length but is always a
4. A rising edge on pin CS indicates the end of data transmission.
the start of communications.
multiple of 8 bits. The Most Significant Bit (MSB) is always sent first (for instruction
and data bytes).
A9
Instruction bytes
A8
A7
A6
All information provided in this document is subject to legal disclaimers.
A5
A4
Rev. 5 — 9 February 2011
A3
A2
A1
A0
D7
D6
D5
Register N (data)
Dual 14-bit ADC; serial JESD204A interface
D4
D3
D2
ADC1413D series
D1
D0
D7
D6
D5
Register N + 1 (data)
D4
© NXP B.V. 2011. All rights reserved.
D3
D2
D1
005aaa086
D0
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