HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 23

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
ADC1413D_SER
Product data sheet
Fig 22. Detailed view of the JESD204A serializer with debug functionality
ADC_PD
ADC_PD
DUMMY
DUMMY
ADC B
ADC A
PRBS
PRBS
AND
DLL
PLL
× 10F
× F
14 + 1
14 + 1
× 1
14 + 1
14 + 1
11.5.2 ADC core output codes versus input voltage
ADC_MODE[1:0]
ADC_MODE[1:0]
frame CLK
character CLK
bit CLK
10
11
11
10
00
00
Table 13
Table 13.
INP  INM (V) Offset binary
< 1
1
0.9998779
0.9997559
0.9996338
0.9995117
....
0.0002441
0.0001221
0
+0.0001221
+0.0002441
....
+0.9995117
14 + 1
14 + 1
AND
AND
CS
CS
ASSEMBLY
N
N
FRAME
shows the data output codes for a given analog input voltage.
Output codes versus input voltage
N + CS
N + CS
00 0000 0000 0000
00 0000 0000 0000
00 0000 0000 0001
00 0000 0000 0010
00 0000 0000 0011
00 0000 0000 0100
....
01 1111 1111 1110
01 1111 1111 1111
10 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0010
....
11 1111 1111 1011
All information provided in this document is subject to legal disclaimers.
replication;
test mode)
assembly,
character
(frame
FSM
ILA,
Rev. 5 — 9 February 2011
PRBS
PRBS
8
sync_request
8
SCR_IN_MODE
SCR_IN_MODE
00
01
01
00
Dual 14-bit ADC; serial JESD204A interface
SCR
SCR
Two’s complement
10 0000 0000 0000
10 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0010
10 0000 0000 0011
10 0000 0000 0100
....
11 1111 1111 1110
11 1111 1111 1111
00 0000 0000 0000
00 0000 0000 0001
00 0000 0000 0010
....
01 1111 1111 1011
ADC1413D series
10-bit
10-bit
8-bit/
8-bit/
PRBS
PRBS
'0/1'
'0/1'
'0'
'0'
LANE_MODE[1:0]
LANE_MODE[1:0]
10
10
00
01
10
11
11
10
01
00
LANE_POL
LANE_POL
SWING_SEL[2:0]
© NXP B.V. 2011. All rights reserved.
SER
SER
005aaa085
23 of 43
OTR
1
0
0
0
0
0
0
0
0
0
0
0
0
0