HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 22

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
ADC1413D_SER
Product data sheet
Fig 21. General overview of the JESD204A serializer
S samples per frame cycle
N bits from Cr
CS bits for control
SYNC~
CS bits for control
N bits from Cr
M CONVERTERS
N' = N+CS
M−1
0
11.5.1 Digital JESD204A formatter
+
+
11.5 JESD204A serializer
Mx(N'xS) bits
lane stream mapping
For more information about the JESD204A standard refer to the JEDEC web site.
The block placed after the ADC cores is used to implement all functionalities of the
JESD204A standard. This ensures signal integrity and guarantees the clock and the data
recovery at the receiver side.
The block is highly parameterized and can be configured in various ways depending on
the sampling frequency and the number of lanes used.
samples stream to
TX transport layer
Fig 20. CML output connection to the receiver (AC-coupled)
HD: frame boundary break
CF: position of control bits
Padding with Tail bits (TT)
L LANES
All information provided in this document is subject to legal disclaimers.
F octets
F octets
+
Lx(F) octets
Rev. 5 — 9 February 2011
OCTETS
OCTETS
FRAME
FRAME
VDDD
TO
TO
12 mA to 26 mA
L octets
50 Ω
−
SCRAMBLER
SCRAMBLER
CMLPA/CMLPB
CMLNA/CMLNB
Dual 14-bit ADC; serial JESD204A interface
10 nF
10 nF
TX CONTROLLER
CHARACTER
GENERATOR
CHARACTER
GENERATOR
ALIGNMENT
ALIGNMENT
ADC1413D series
100 Ω
10-bit
10-bit
8-bit/
8-bit/
RECEIVER
005aaa083
© NXP B.V. 2011. All rights reserved.
005aaa084
SER
SER
LANE 0
LANE 1
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