HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 24

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
ADC1413D_SER
Product data sheet
11.6.1 Register description
11.6 Serial Peripheral Interface (SPI)
Table 13.
The ADC1413D serial interface is a synchronous serial communications port allowing
easy interfacing with many industry microprocessors. It provides access to the registers
that control the operation of the chip in both read and write modes.
This interface is configured as a 3-wire type (SDIO as bidirectional pin).
SCLK acts as the serial clock, and pin CS acts as the serial chip select.
Each read/write operation is sequenced by the CS signal and enabled by a LOW level to
to drive the chip with 2 bytes to 5 bytes, depending on the content of the instruction byte
(see
Table 14.
[1]
Table 15.
[1]
Table 16.
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is incremented to access subsequent addresses.
INP  INM (V) Offset binary
+0.9996338
+0.9997559
+0.9998779
+1
> +1
Bit
Description
R/W
W1
0
0
1
1
0
1
R/W indicates whether a read (logic 1) or write (logic 0) transfer occurs after the instruction byte.
Bits W1 and W0 indicate the number of bytes transferred after the instruction byte.
[1]
Table
Output codes versus input voltage
SPI instruction bytes
Read or Write mode access description
Number of bytes to be transferred
14).
11 1111 1111 1100
11 1111 1111 1101
11 1111 1111 1110
11 1111 1111 1111
11 1111 1111 1111
All information provided in this document is subject to legal disclaimers.
Description
Write mode operation
Read mode operation
MSB
7
R/W
A7
[1]
Rev. 5 — 9 February 2011
6
W1
A6
W0
0
1
0
1
5
W0
A5
Dual 14-bit ADC; serial JESD204A interface
…continued
4
A12
A4
Two’s complement
01 1111 1111 1100
01 1111 1111 1101
01 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1111
ADC1413D series
3
A11
A3
Number of bytes transferred
1 byte
2 bytes
3 bytes
4 or more bytes
2
A10
A2
© NXP B.V. 2011. All rights reserved.
1
A9
A1
LSB
0
A8
A0
24 of 43
OTR
0
0
0
0
1