HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 32

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

NXP Semiconductors
Table 30.
Default values are highlighted.
Table 31.
Default values are highlighted.
Table 32.
Default values are highlighted.
ADC1413D_SER
Product data sheet
Bit
7
6
5
4
3
2
1
0
Bit
7 to 2
1
0
Bit
7 to 3
2 to 0
Symbol
-
TRISTATE_CFG_PINS
SYNC_POL
SYNC_SINGLE_ENDED R/W
-
REV_SCR
REV_ENCODER
REV_SERIAL
Symbol
-
SWAP_LANE_0_1
SWAP_ADC_A_B
Symbol
-
SWING_SEL[2:0]
Ser_Control1 (address 0805h)
Ser_Control2 (address 0806h)
Ser_Analog_Ctrl (address 0808h)
R/W
R/W
-
-
-
-
R/W
-
Access
-
-
Access
R/W
Access
R/W
All information provided in this document is subject to legal disclaimers.
000000
Value
0
1
0
1
0
1
1
0
1
0
1
0
1
Value
0
1
0
1
Value
00000
011
Rev. 5 — 9 February 2011
LSBs are swapped with MSBs at the 8-bit/10-bit encoder input:
LSBs are swapped with MSBs at the lane input:
Description
not used
defines the sync signal polarity:
defines the input mode of the sync signal:
not used
LSBs are swapped with MSBs at the scrambler input:
Description
not used
swaps the outputs of the JESD204A unit. (output buffer A is
connected to Lane 1, output buffer B is connected to Lane 0):
swaps the inputs of the JESD204A unit. (ADC A output is
connected to input B, ADC B is connected to input A):
Description
not used
defines the swing output for the lane pads
pins CFG3 to CFG0 are set to high-impedance. Switch to 0
automatically after start-up or reset.
synchronization signal is active LOW
synchronization signal is active HIGH
synchronization input mode is set in Differential mode
synchronization input mode is set in Single-ended mode
disable
enable
disable
enable
disable
enable
disable
enable
disable
enable
Dual 14-bit ADC; serial JESD204A interface
ADC1413D series
© NXP B.V. 2011. All rights reserved.
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