ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 105

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

DDC INTERFACE (Cont’d)
Once the DDC1/2B Interface has acknowledged a
write transfer request, i.e. a Device Address with
RW=0, it waits for a data address. When the latter
is received, it is acknowledged and loaded into the
ALR.
Then, the master may send any number of data
bytes that are all acknowledged by the DDC1/2B
Interface. The data bytes are written in RAM if the
WP bit=0 in the DCR register, otherwise the RAM
location is not modified.
In any case, all write operations are performed
in RAM and therefore do not delay DDC
transfers,
execution is halted for 2 cycles.
Figure 65. Write sequence
All read operations consist of retrieving the data
pointed to by an internal address counter which is
initialized by a dummy write and incremented by
any read. The DDC1/2B Interface always waits for
an acknowledge during the 9th bit-time. If the
master does not pull the SDA line low during this
bit-time, the DDC1/2B Interface ends the transfer
and switches to a stand-by state.
– Current address read: After generating a
START condition the master sends a read device
address (RW = 1). The DDC1/2B Interface ac-
knowledges this and outputs the data byte point-
ed to by the internal address pointer which is
subsequently incremented. The master must
NOT acknowledge this byte and must terminate
the transfer with a STOP condition.
Addr.
Pointer
Write Operation
Read Operations
SDA
although
DEV ADDR
XXXXh
concurrent
DATA ADDR.
software
DATA IN 1
ADDR
After each byte is transferred, the internal address
counter is automatically incremented.
If the counter is pointing to the top of the structure,
it rolls over to the bottom since the incrementation
is performed only on the 7 or 8 LSB’s of the pointer
depending on the selected data structure size. In
other words, ALR rolls over from FFh to 00h for
Device
Otherwise, it rolls over from 7Fh to 00h or from FFh
to 80h depending on the MSB of the last data
address received.
Then after that last byte has been effectively
written in RAM, the EDF flag is set and an interrupt
is generated if EDE is set.
The transfer is terminated by the master
generating a STOP condition.
– Random address read: The master performs a
– Sequential address read: This mode is similar
dummy write to load the data address into the
ALR. Then the master sends a RESTART condi-
tion followed by a read Device Address (RW=1).
to the current and random address reads, except
that the master DOES acknowledge the data
byte for the DDC1/2B Interface to output the next
byte in sequence. To terminate the read opera-
tion the master must NOT acknowledge the last
data byte and must generate a STOP condition.
The data output are from consecutive memory
addresses. The internal address counter is incre-
mented automatically after each byte. If the
counter is pointing to the top of the structure, it
rolls over to the bottom since the incrementation
is performed only on the 7 or 8 LSB’s of the
counter depending on the selected data structure
size.
Addresses
DATA IN 2
ADDR + 1
ST72774/ST727754/ST72734
A2h/A3h
ADDR + n -1
DATA IN n
and
ADDR + n
A6h/A7h.
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