ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 41

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

4.3 16-BIT TIMER (TIM)
4.3.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
pulse length measurement of up to two input
signals ( input capture ) or generation of up to two
output waveforms ( output compare and PWM ).
Pulse lengths and waveform periods can be
modulated from a few microseconds to several
milliseconds using the timer prescaler and the
CPU clock prescaler.
4.3.2 Main Features
The Block Diagram is shown in
Note: Some external pins are not available on all devices.
Programmable prescaler: f
8.
Overflow status flag and maskable interrupt
External clock input (must be at least 4 times
slower than the CPU clock speed) with the
choice of active edge
Output compare functions with
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
Input capture functions with
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
Pulse width modulation mode (PWM)
One pulse mode
5 alternate functions on I/O ports*
Refer to the device pin out description.
cpu
Figure
divided by 2, 4 or
27.
4.3.3 Functional Description
4.3.3.1 Counter
The principal block of the Programmable Timer is a
16-bit free running counter and its associated 16-
bit registers:
Counter Registers
Alternate Counter Registers
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (overflow
flag), (see note
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in
Control
repeats every 131.072, 262.144 or 524.288
internal processor clock cycles depending on the
CC1 and CC0 bits.
– Counter High Register (CHR) is the most sig-
– Counter Low Register (CLR) is the least sig-
– Alternate Counter High Register (ACHR) is the
– Alternate Counter Low Register (ACLR) is the
nificant byte (MSB).
nificant byte (LSB).
most significant byte (MSB).
least significant byte (LSB).
Bits. The value in the counter register
page
ST72774/ST727754/ST72734
43).
Table 15 Clock
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