ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 14

ST72T774J9B1

Manufacturer Part Number
ST72T774J9B1
Description
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72T774J9B1

Cpu Family
ST7
Device Core Size
8b
Frequency (max)
24MHz
Interface Type
I2C/USB
Program Memory Type
EPROM
Program Memory Size
60KB
Total Internal Ram Size
1KB
# I/os (max)
31
Number Of Timers - General Purpose
1
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4V
On-chip Adc
1-chx8-bit
On-chip Dac
1-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
42
Package Type
SPDIP
Lead Free Status / Rohs Status
Specific Sites Compliant

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ST72774/ST727754/ST72734
1.4 External connections
The following figure shows the recommended ex-
ternal connections for the device.
The V
and EPROM devices and must be tied to ground in
user mode.
The 10 nF and 0.1 µF decoupling capacitors on
the power supply lines are a suggested EMC per-
formance/cost tradeoff.
Figure 4. Recommended External Connections
14/144
PP
pin is only used for programming OTP
EXTERNAL RESET CIRCUIT
V
DD
Or configure unused I/O ports
by software as input with pull-up
10nF
0.1µF
0.1µF
V
DD
+
V
DD
4.7K
0.1µF
10K
1K
See
Clocks
Section
The external reset network (including the manda-
tory 1K serial resistor) is intended to protect the
device against parasitic resets, especially in noisy
environments.
Unused I/Os should be tied high to avoid any un-
necessary power consumption on floating lines.
An alternative solution is to program the unused
ports as inputs with pull-up.
V
V
V
RESET
Unused I/O
OSCOUT
OSCIN
PP
DD
SS

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