ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 51

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

4.3.4 Register Description
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the
alternate counter.
CONTROL REGISTER 1 (CR1)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = ICIE Input Capture Interrupt Enable.
Bit 6 = OCIE Output Compare Interrupt Enable.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
7
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the
ICF1 or ICF2 bit of the SR register is set.
OCF1 or OCF2 bit of the SR register is set.
TOF bit of the SR register is set.
0
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is not cleared by software, only by a chip
reset.
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is not cleared by software, only by a chip
reset.
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R
register and OCxE is set in the CR2 register. This
value is copied to the OCMP1 pin in One Pulse
Mode and Pulse Width Modulation mode.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition on
the ICAP1 pin will trigger the capture.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin
whenever a successful comparison occurs with
the OC1R register and the OC1E bit is set in the
CR2 register.
0: No effect.
1:Forces the OLVL2 bit to be copied to the
0: No effect.
1: Forces OLVL1 to be copied to the OCMP1
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
OCMP2 pin.
pin.
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