ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 52

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

ST72774/ST727754/ST72734
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = OC1E Output Compare 1 Enable.
Bit 6 = OC2E Output Compare 2 Enable.
Bit 5 = OPM One Pulse Mode.
Bit 4 = PWM Pulse Width Modulation.
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OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
0: Output Compare 1 function is enabled, but
1: Output Compare 1 function is enabled, the
0: Output Compare 2 function is enabled, but
1: Output Compare 2 function is enabled, the
0: One Pulse Mode is not active.
1: One Pulse Mode is active, the ICAP1 pin can
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs
7
the OCMP1 pin is a general I/O.
OCMP1 pin is dedicated to the Output Com-
pare 1 capability of the timer.
the OCMP2 pin is a general I/O.
OCMP2 pin is dedicated to the Output Com-
pare 2 capability of the timer.
be used to trigger one pulse on the OCMP1
pin; the active transition is given by the
IEDG1 bit. The length of the generated pulse
depends on the contents of the OC1R regis-
ter.
a programmable cyclic signal; the length of
the pulse depends on the value of OC1R reg-
ister; the period depends on the value of
OC2R register.
0
Bit 3, 2 = CC1-CC0 Clock Control.
The value of the timer clock depends on these bits:
Table 15. Clock Control Bits
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition on
the ICAP2 pin will trigger the capture.
Bit 0 = EXEDG External Clock Edge.
This bit determines which type of level transition on
the external clock pin EXTCLK will trigger the free
running counter.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
0: A falling edge triggers the free running coun-
1: A rising edge triggers the free running coun-
CC1
ter.
ter.
0
0
1
1
CC0
0
1
0
1
External Clock (where
Timer Clock
available)
f
f
f
CPU
CPU
CPU
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