ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 49

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

16-BIT TIMER (Cont’d)
4.3.3.5 Forced Compare Mode
In this section i may represent 1 or 2.
The following bits of the CR1 register are used:
When the FOLV i bit is set, the OLVL i bit is copied
to the OCMP i pin. The FOLV i bit is not cleared by
software, only by a chip reset. The OLV i bit has to
be toggled in order to toggle the OCMP i pin when
it is enabled (OC i E bit=1).
The OCF i bit is not set, and thus no interrupt
request is generated.
4.3.3.6 One Pulse Mode
One Pulse mode enables the generation of a pulse
when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
Procedure
To use one pulse mode, select the following in the
the CR1 register:
– Using the OLVL1 bit, select the level to be ap-
– Using the OLVL2 bit, select the level to be ap-
– Select the edge of the active transition on the
And select the following in the CR2 register:
– Set the OC1E bit, the OCMP1 pin is then dedi-
Figure 35.
plied to the OCMP1 pin after the pulse.
plied to the OCMP1 pin during the pulse.
ICAP1 pin with the IEDG1 bit .
cated to the Output Compare 1 function.
COUNTER
One
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
OCMP1
ICAP1
FOLV2 FOLV1 OLVL2
Pulse Mode Timing
....
FFFC FFFD FFFE
OLVL2
OLVL1
– Set the OPM bit.
– Select the timer clock CC1-CC0 (see
Load
corresponding to the length of the pulse (see the
formula in
Then, on a valid event on the ICAP1 pin, the
counter is initialized to FFFCh and OLVL2 bit is
loaded on the OCMP1 pin. When the value of the
counter is equal to the value of the contents of the
OC1R register, the OLVL1 bit is output on the
OCMP1 pin, (See
Note: The OCF1 bit cannot be set by hardware in one
The ICF1 bit is set when an active edge occurs and
can generate an interrupt if the ICIE bit is set.
When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
Clock Control
compare1
2ED0 2ED1 2ED2
pulse mode but the OCF2 bit can generate an Out-
put Compare interrupt.
event occurs
the
on ICAP1
Counter
= OC1R
When
When
Section
OC1R
OLVL1
Bits).
ST72774/ST727754/ST72734
2ED3
Figure
4.3.3.7).
One pulse mode cycle
register
35).
OCMP1 = OLVL2
OCMP1 = OLVL1
FFFC FFFD
Counter is
initialized
to FFFCh
OLVL2
with
the
Table 15
49/144
value