ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 57

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

SYNC PROCESSOR (SYNC) (Cont’d)
4.4.3 Input Signals
The Sync Processor has the following inputs (TTL
level):
– VSYNCI1 Vertical Sync input1
– HSYNCI1 Horizontal Sync input1 or Composite
– VSYNCI2 Vertical Sync input2
– HSYNCI2 Horizontal Sync input2 or Composite
Note: The above input pairs can be used for DSUB or
– CSYNCI Sync on Green (external extractor)
Note: If the CSYNCI pin is needed for another I/O func-
– HFBACK Horizontal Flyback input
– VFBACK Vertical Flyback input
4.4.4 Input Signal Waveforms
– The input signals must contain only synchroniza-
– The VSYNCI signal is internally connected to
– The HSYNCI or CSYNCI signal, prescaled by
– Typical timing range: See
– If the timer clock is 2 MHz (external oscillator fre-
(PV= Vertical pulse, PH = Horizontal pulse)
sync
sync
tion pulses. In case of serration pulses on CSYN-
CI/HSYNCI, the pulse width should be less than
8µs.
Timer Input Capture 1 (ICAP1).
256, is internally connected to Timer Input Cap-
ture 2 (ICAP2).
quency 24 MHz):
PV accuracy = +/- 1 Timer clock (500ns)
PH*256 accuracy = +/- 1 Timer clock (500ns)
BNC connectors. To select these inputs use the
HVSEL bit in the POLR register.
tion, the composite sync signal can be connected to
HSYNCI using the SCI0 bit in the MCR register.
Figure 38
and
39
4.4.5 Output Signals
The Sync Processor has the following outputs:
HSYNCO Horizontal Sync Output
Enable: SYNOP bit in ENR register
Programmable polarity:
In case of composite sync signal, the signal can be
blanked by software during the vertical period
(HINH bit in ENR register).
In case of separate sync, no blanking is generated.
VSYNCO Vertical Sync Output
Enable: SYNOP bit in ENR register
Programmable polarity:
In case of composite sync the delay of the
extracted Vsync signal is:
minimum: 500ns + HSYNCO pulse width
maximum: 8750ns (max. threshold in ex-
HS0/HS1 bits in MCR register
VOP bit in the MCR register
traction mode)
ST72774/ST727754/ST72734
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