PSB 21393 H V1.3 Infineon Technologies, PSB 21393 H V1.3 Datasheet - Page 107

• Manufacturer Part Number: PSB 21393 H V1.3
• Description: IC CODEC W/TRANSCEIVER MQFP-44
• Manufacturer: Infineon Technologies
• Series: SCOUT™r

Specifications of PSB 21393 H V1.3

• Function: CODEC
• Interface: IOM-2, SCI, UPN
• Number Of Circuits: 1
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 27mA
• Mounting Type: Surface Mount
• Package / Case: 44-BQFP
• Includes: Activation and Deactivation, Channel Handler, DTMF / Tone / Ringing Generator, HDLC Controller, Speakerphone, UPN Transceiver
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Operating Temperature: -
• Other names: PSB21393HV1.3XT; PSB21393HV13XP; SP000007533; SP000007534

The XFIFO requests service from the microcontroller by setting a bit in the ISTAH
register, which causes an interrupt (XPR, XDU, XMR). The microcontroller can then read
the status register STAR (XFW, XDOV), write data in the FIFO and it can change the
transmit FIFO block size (EXMR.XFBS) if required.
The instant of the initiation of a transmit pool ready (XPR) interrupt after different transmit
control commands is listed in table 9.
Table 9
XPR Interrupt (availability of the XFIFO) after XTF, XME Commands
When setting XME the transmitter appends the FCS and the end flag at the end of the
frame. When XTF & XME has been set, the XFIFO is locked until successful
transmission of the current frame, so a consecutive XPR interrupt also indicates
successful transmission of the frame whereas after XME or XTF the XPR interrupt is
asserted as soon as there is space for one data block in the XFIFO.
The transfer block size is 32 bytes by default, but sometimes, if the microcontroller has
a high computational load, it is useful to increase the maximum reaction time for an XPR
interrupt. The maximum reaction time is:
t
A selected block size of 16 bytes means that an XPR interrupt is indicated when there
are still 48 bytes (64 bytes - 16 bytes) to be transmitted. With a 32 bytes block size the
XPR is initiated when there are still 32 bytes (64 bytes - 32 bytes), i.e. the maximum
reaction time for the smaller block size is 50 % higher with the trade-off of a doubled
interrupt load. A selected block size of 32 or 16 bytes respectively always indicates the
available space in the XFIFO. So any number of bytes smaller than the selected XFBS
may be stored in the FIFO during one “write block“ access cycle.
Similar to RFBS for the receive FIFO, a new setting of XFBS takes effect after the next
XTF,XME or XRES command. XRES resets the XFIFO.
The XFIFO can hold any number of frames fitting in the 64 bytes.
Data Sheet
max
CMDR.
XTF
XTF &
XME
XME
= (XFIFO size - XFBS) / data transmission rate
Transmit pool ready (XPR) interrupt initiated...
as soon as the selected buffer size in the FIFO is available
after the successful transmission of the closing flag. The transmitter
sends always an abort sequence
as soon as the selected buffer size in the FIFO is available, two
consecutive frames share flags
97
HDLC Controller
PSB 21391
PSB 21393
2001-03-07