PSB 21393 H V1.3 Infineon Technologies, PSB 21393 H V1.3 Datasheet - Page 37

• Manufacturer Part Number: PSB 21393 H V1.3
• Description: IC CODEC W/TRANSCEIVER MQFP-44
• Manufacturer: Infineon Technologies
• Series: SCOUT™r

Specifications of PSB 21393 H V1.3

• Function: CODEC
• Interface: IOM-2, SCI, UPN
• Number Of Circuits: 1
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 27mA
• Mounting Type: Surface Mount
• Package / Case: 44-BQFP
• Includes: Activation and Deactivation, Channel Handler, DTMF / Tone / Ringing Generator, HDLC Controller, Speakerphone, UPN Transceiver
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Operating Temperature: -
• Other names: PSB21393HV1.3XT; PSB21393HV13XP; SP000007533; SP000007534

Five interrupt bits in the ISTA register point at interrupt sources in the HDLC Controller
(HDLC), Monitor- (MOS) and C/I- (CIC) handler, the transceiver (TRAN) and the
synchronous transfer (ST). The timer interrupt (TIN) and the watchdog timer overflow
(WOV) can be read directly from the ISTA register. All these interrupt sources are
described in the corresponding chapters. After the SCOUT has requested an interrupt
by setting its INT pin to low, the host must read first the SCOUT interrupt status register
(ISTA) in the associated interrupt service routine. The INT pin of the SCOUT remains
active until all interrupt sources are cleared by reading the corresponding interrupt
register. Therefore it is possible that the INT pin is still active when the interrupt service
routine is finished.
Each interrupt indication of the interrupt status registers can selectively be masked by
setting the respective bit in the MASK register.
For some interrupt controllers or hosts it might be necessary to generate a new edge on
the interrupt line to recognize pending interrupts. This can be done by masking all
interrupts at the end of the interrupt service routine (writing FF
and write back the old mask to the MASK register.
A low level at pin EAW generates an interrupt indication which is set at the LD bit of the
ISTATR register. If this LD bit has been set due to an level detect interrupt, the LD bit in
the transceiver status register TR_STA is set additionally.
Therefore pin EAW has to be connected to ’1’, if no interrupt should be generated.
Data Sheet
27
H
into the MASK register)
PSB 21391
PSB 21393
Interfaces
2001-03-07