PSB 21393 H V1.3 Infineon Technologies, PSB 21393 H V1.3 Datasheet - Page 202

• Manufacturer Part Number: PSB 21393 H V1.3
• Description: IC CODEC W/TRANSCEIVER MQFP-44
• Manufacturer: Infineon Technologies
• Series: SCOUT™r

Specifications of PSB 21393 H V1.3

• Function: CODEC
• Interface: IOM-2, SCI, UPN
• Number Of Circuits: 1
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 27mA
• Mounting Type: Surface Mount
• Package / Case: 44-BQFP
• Includes: Activation and Deactivation, Channel Handler, DTMF / Tone / Ringing Generator, HDLC Controller, Speakerphone, UPN Transceiver
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Operating Temperature: -
• Other names: PSB21393HV1.3XT; PSB21393HV13XP; SP000007533; SP000007534

Data Sheet
7.1.9
Value after reset: 7F
MASK
For the MASK register following logical states are applied:
0: Interrupt is not masked
1: Interrupt is masked
Each interrupt source in the ISTA register can be selectively masked by setting to ’1’ the
corresponding bit in MASK. Masked interrupt status bits are not indicated when ISTA is
read. Instead, they remain internally stored and pending, until the mask bit is reset to ’0’.
Note: In the event of a C/I channel change, CIC is set in ISTA even if the corresponding
7.1.10
Value after reset: 00
MODE1
MCLK
The Master Clock Frequency bits control the microcontroller clock output corresponding
following table.
Bit 7 Bit 6 MCLK frequency
0
0
1
1
mask bit in MASK is active, but no interrupt is generated.
0
1
0
1
MASK - Mask Register
MODE1 - Mode1 Register
7
7
MODE1.CDS = ’0’
0
MCLK
... Master Clock Frequency
3.84 MHz
0.96 MHz
7.68 MHz
disabled
with
H
H
ST
CDS WTC1 WTC2
CIC
MODE1.CDS = ’1’
MCLK frequency
TIN
15.36 MHz
7.68 MHz
1.92 MHz
disabled
with
192
WOV TRAN MOS HDLC
CFS
Detalled Register Description
RSS2 RSS1 RD/WR (3D
0
0
PSB 21391
PSB 21393
2001-03-07
WR (3C
H
H
)
)