PSB 21393 H V1.3 Infineon Technologies, PSB 21393 H V1.3 Datasheet - Page 98

• Manufacturer Part Number: PSB 21393 H V1.3
• Description: IC CODEC W/TRANSCEIVER MQFP-44
• Manufacturer: Infineon Technologies
• Series: SCOUT™r

Specifications of PSB 21393 H V1.3

• Function: CODEC
• Interface: IOM-2, SCI, UPN
• Number Of Circuits: 1
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 27mA
• Mounting Type: Surface Mount
• Package / Case: 44-BQFP
• Includes: Activation and Deactivation, Channel Handler, DTMF / Tone / Ringing Generator, HDLC Controller, Speakerphone, UPN Transceiver
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Operating Temperature: -
• Other names: PSB21393HV1.3XT; PSB21393HV13XP; SP000007533; SP000007534

Data Sheet
3.2
3.2.1
3.2.1.1
The 64-byte cyclic RFIFO buffer has variable FIFO block sizes (thresholds) of 4, 8, 16 or
32 bytes which can be selected by setting the corresponding RFBS bits in the EXMR
register. The variable block size allows an optimized HDLC processing concerning frame
length, I/O throughput and interrupt load.
The transfer protocol between HDLC FIFO and microcontroller is block orientated with
the microcontroller as master. The control of the data transfer between the CPU and the
HDLC controller is handled via interrupts (HDLC controller
(Host
There are three different interrupt indications in the ISTAH register concerned with the
reception of data:
– RPF (Receive Pool Full) interrupt, indicating that a data block of the selected length
– RME (Receive Message End) interrupt, indicating that the reception of one message
– RFO (Receive Frame Overflow) interrupt, indicating that a complete frame could not
There are two control commands (bits of CMDR) that are used with the reception of data:
– RMC (Receive Message Complete) command, telling the HDLC controller that a data
– RRES (Receiver Reset) command, resetting the HDLC receiver and clearing the
(EXMR.RFBS) can be read from RFIFO. The message which is currently received
exceeds the block size so further blocks will be received to complete the message.
is completed, i.e. either
• a short message is received
• the last part of a long message is received
be stored in RFIFO and is therefore lost as the RFIFO is occupied. This occurs if the
host fails to respond quickly enough to RPF/RME interrupts since previous data was
not read by the host.
block has been read from the RFIFO and the corresponding FIFO space can be
released for new receive data.
receive FIFO of any data (e.g. used before start of reception). It has to be used after
having changed the mode.
(message length
(message length
and is stored in the RFIFO.
HDLC controller).
Data Reception
Structure and Control of the Receive FIFO
General Description
the defined block size (EXMR.RFBS) or
the defined block size (EXMR.RFBS))
88
Host) and commands
HDLC Controller
PSB 21391
PSB 21393
2001-03-07