PSB 21393 H V1.3 Infineon Technologies, PSB 21393 H V1.3 Datasheet - Page 167

• Manufacturer Part Number: PSB 21393 H V1.3
• Description: IC CODEC W/TRANSCEIVER MQFP-44
• Manufacturer: Infineon Technologies
• Series: SCOUT™r

Specifications of PSB 21393 H V1.3

• Function: CODEC
• Interface: IOM-2, SCI, UPN
• Number Of Circuits: 1
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 27mA
• Mounting Type: Surface Mount
• Package / Case: 44-BQFP
• Includes: Activation and Deactivation, Channel Handler, DTMF / Tone / Ringing Generator, HDLC Controller, Speakerphone, UPN Transceiver
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Operating Temperature: -
• Other names: PSB21393HV1.3XT; PSB21393HV13XP; SP000007533; SP000007534

5
Figure 78 shows the clock system of the SCOUT. The oscillator is used to generate a
15.36 MHz clock signal. The DPLL generates the IOM-2 clocks FSC (8 kHz), DCL (1536
kHz) and BCL (768 kHz) synchronous to the received U
The prescaler for the microcontroller clock output (MCLK) divides the 15.36 MHz clock
by 1, 2 and 8 corresponding to the MCLK control bits in the MODE1 register. Additionally
it is possible to disable the MCLK output by setting the MCLK bits to ’11’. With the CDS
bit (Clock Divider Selection) in the MODE1 register a double clock rate for the MCLK
output can be selected.
.
Figure 78
Clock System of the SCOUT
Data Sheet
15.36 MHz
Clock Generation
XTAL
MODE1.CDS =
'0': x = 2
'1': x = 1
OSC
15.36 MHz
x
MODE1.MCLK
C/I change
EAW
Watchdog
Undervoltage Detection
'00':
'01':
'10':
'11':
DPLL
Reset Generation
MCLK Prescaler
157
2
8
1
MCLK disabled
CPLL
3
PN
frames (see figure 79).
FSC
DCL
BCL
Codec
Clock
125 µs < t < 250 µs
125 µs < t < 250 µs
t = 125 µs
t = 64 ms
MCLK
clock_gen_p.vsd
Clock Generation
PSB 21391
PSB 21393
2001-03-07