CY8C5248LTI-030 Cypress Semiconductor Corp, CY8C5248LTI-030 Datasheet - Page 12

• Manufacturer Part Number: CY8C5248LTI-030
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5248LTI-030

• Lead Free Status / Rohs Status: Compliant

4.3.3 Priority Levels
The CPU always has higher priority than the DMA controller
when their accesses require the same bus resources. Due to the
system architecture, the CPU can never starve the DMA. DMA
channels of higher priority (lower priority number) may interrupt
current DMA transfers. In the case of an interrupt, the current
transfer is allowed to complete its current transaction. To ensure
latency limits when multiple DMA accesses are requested
simultaneously, a fairness algorithm guarantees an interleaved
minimum percentage of bus bandwidth for priority levels 2
through 7. Priority levels 0 and 1 do not take part in the fairness
algorithm and may use 100% of the bus bandwidth. If a tie occurs
on two DMA requests of the same priority level, a simple round
robin method is used to evenly share the allocated bandwidth.
The round robin allocation can be disabled for each DMA
channel, allowing it to always be at the head of the line. Priority
levels 2 to 7 are guaranteed the minimum bus bandwidth shown
in
satisfied their requirements.
When the fairness algorithm is disabled, DMA access is granted
based solely on the priority level; no bus bandwidth guarantees
are made.
4.3.4 Transaction Modes Supported
The flexible configuration of each DMA channel and the ability to
chain multiple channels allow the creation of both simple and
complex use cases. General use cases include, but are not
limited to:
4.3.4.2 Auto Repeat DMA
Auto repeat DMA is typically used when a static pattern is
repetitively read from system memory and written to a peripheral.
This is done with a single TD that chains to itself.
4.3.4.3 Ping Pong DMA
A ping pong DMA case uses double buffering to allow one buffer
to be filled by one client while another client is consuming the
data previously received in the other buffer. In its simplest form,
this is done by chaining two TDs together so that each TD calls
the opposite TD when complete.
4.3.4.4 Circular DMA
Circular DMA is similar to ping pong DMA except it contains more
than two buffers. In this case there are multiple TDs; after the last
TD is complete it chains back to the first TD.
Document Number: 001-66236 Rev. *A
ADDR 16/32
Table 4-4
READY
WRITE
DATA
CLK
after the CPU and DMA priority levels 0 and 1 have
ADDRESS Phase
Basic DMA Read Transfer without wait states
A
DATA Phase
PRELIMINARY
B
Figure 4-2. DMA Timing Diagram
DATA (A)
ADDR 16/32
Table 4-4. Priority Levels
4.3.4.1 Simple DMA
In a simple DMA case, a single TD transfers data between a
source and sink (peripherals or memory location). The basic
timing diagrams of DMA read and write cycles are shown in
Figure
to the Technical Reference Manual.
4.3.4.5 Indexed DMA
In an indexed DMA case, an external master requires access to
locations on the system bus as if those locations were shared
memory. As an example, a peripheral may be configured as an
SPI or I
master. That address becomes an index or offset into the internal
system bus memory space. This is accomplished with an initial
“address fetch” TD that reads the target address location from
the peripheral and writes that value into a subsequent TD in the
chain. This modifies the TD chain on the fly. When the “address
fetch” TD completes it moves on to the next TD, which has the
new address information embedded in it. This TD then carries
out the data transfer with the address location required by the
external master.
READY
WRITE
DATA
PSoC
Priority Level
CLK
4-2. For more description on other transfer modes, refer
2
C slave where an address is received by the external
0
1
2
3
4
5
6
7
®
ADDRESS Phase
5: CY8C52 Family Datasheet
Basic DMA Write Transfer without wait states
A
% Bus Bandwidth
100.0
100.0
50.0
25.0
12.5
6.2
3.1
1.5
DATA Phase
DATA (A)
B
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