CY8C5248LTI-030 Cypress Semiconductor Corp, CY8C5248LTI-030 Datasheet - Page 23

• Manufacturer Part Number: CY8C5248LTI-030
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5248LTI-030

• Lead Free Status / Rohs Status: Compliant

Figure 6-5. Power Mode Transitions
6.2.1.1 Active Mode
Active mode is the primary operating mode of the device. When
in active mode, the active configuration template bits control
which available resources are enabled or disabled. When a
resource is disabled, the digital clocks are gated, analog bias
currents are disabled, and leakage currents are reduced as
appropriate. User firmware can dynamically control subsystem
power by setting and clearing bits in the active configuration
template. The CPU can disable itself, in which case the CPU is
automatically reenabled at the next wakeup event.
When a wakeup event occurs, the global mode is always
returned to active, and the CPU is automatically enabled,
regardless of its template settings. Active mode is the default
global power mode upon boot.
6.2.1.2 Alternate Active Mode
Alternate Active mode is very similar to Active mode. In alternate
active mode, fewer subsystems are enabled, to reduce power
consumption. One possible configuration is to turn off the CPU
and flash, and run peripherals at full speed.
6.2.1.3 Sleep Mode
Sleep mode reduces power consumption when a resume time of
15 µs is acceptable. The wake time is used to ensure that the
regulator outputs are stable enough to directly enter active
mode.
6.2.1.4 Hibernate Mode
In hibernate mode nearly all of the internal functions are
disabled. Internal voltages are reduced to the minimal level to
keep vital systems alive. Configuration state is preserved in
hibernate mode and SRAM memory is retained. GPIOs
configured as digital outputs maintain their previous values and
external GPIO pin interrupt settings are preserved. The device
can only return from hibernate mode in response to an external
I/O interrupt. The resume time from hibernate mode is less than
100 µs.
6.2.1.5 Wakeup Events
Wakeup events are configurable and can come from an interrupt
or device reset. A wakeup event restores the system to active
mode. Interrupt sources include internally generated interrupts,
Document Number: 001-66236 Rev. *A
Manual
Alternate
Active
Active
Sleep
Hibernate
PRELIMINARY
power supervisor, central timewheel, and I/O interrupts. The
central timewheel provides periodic interrupts to allow the
system to wake up, poll peripherals, or perform real-time
functions. Reset event sources include the external reset I/O pin
(XRES) and WDT.
6.2.2 Boost Converter
Applications that use a supply voltage of less than 2.7 V, such as
solar or single cell battery supplies, may use the on-chip boost
converter. The boost converter may also be used in any system
that requires a higher operating voltage than the supply provides.
For instance, this includes driving 5.0 V LCD glass in a 3.3 V
system. The boost converter accepts an input voltage as low as
1.8 V. With one low cost inductor it produces a selectable output
voltage sourcing enough current to operate the PSoC and other
on-board components.
The boost converter accepts an input voltage V
3.6 V, and can start up with V
provides a user configurable output voltage of 3.3 to 5.0 V
(V
than or equal to V
The block can deliver up to 50 mA (I
configuration.
Four pins are associated with the boost converter: V
V
V
inputs. An inductor is connected between the V
The designer can optimize the inductor value to increase the
boost converter efficiency based on input voltage, output
voltage, current and switching frequency. The External Schottky
diode shown in
V
Figure 6-6. Application for Boost Converter
The switching frequency can be set to 100 kHz, 400 kHz, 2 MHz,
or 32 kHz to optimize efficiency and component cost. The
100 kHz, 400 kHz, and 2 MHz switching frequencies are
generated using oscillators internal to the boost converter block.
When the 32 KHz switching frequency is selected, the clock is
derived from a 32 kHz external crystal oscillator. The 32 KHz
external clock is primarily intended for boost standby mode.
At 2 MHz the Vboost output is limited to 2 × Vbat, and at 400 kHz
Vboost is limited to 4 × Vbat.
BOOST
BOOST
BOOST
required when Vdd
Optional Schottky
BOOST
PSoC
Diode. Only
>3.6 V.
, and Ind. The boosted output voltage is sensed at the
>3.6 V.
pin and must be connected directly to the chip’s supply
). V
BAT
®
22
µF
Figure 6-6
5: CY8C52 Family Datasheet
is typically less than V
BOOST
10 µH
, then V
V
IND
V
V
is required only in cases when
boost
ssb
bat
BAT
V
BOOST
dda
PSoC
as low as 1.8 V. The converter
V
BOOST
ddd
V
V
will be the same as V
BOOST
ssa
ssd
µF
22
) depending on
; if V
0.1
µF
BAT
BAT
Page 23 of 95
BAT
and Ind pins.
from 1.8 V to
BAT
is greater
, V
SSB
BAT
,
.