CY8C5248LTI-030 Cypress Semiconductor Corp, CY8C5248LTI-030 Datasheet - Page 14

• Manufacturer Part Number: CY8C5248LTI-030
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5248LTI-030

• Lead Free Status / Rohs Status: Compliant

4.4 Interrupt Controller
The Cortex-M3 NVIC supports 16 system exceptions and 32 interrupts from peripherals, as shown in
Table 4-5. Cortex-M3 Exceptions and Interrupts
Bit 0 of each exception vector indicates whether the exception is
executed using ARM or Thumb instructions. Because the
Cortex-M3 only supports Thumb instructions, this bit must
always be 1. The Cortex-M3 non maskable interrupt (NMI) input
can be routed to any pin, via the DSI, or disconnected from all
pins. See
page 38.
The Nested Vectored Interrupt Controller (NVIC) handles
interrupts from the peripherals, and passes the interrupt vectors
to the CPU. It is closely integrated with the CPU for low latency
interrupt handling. Features include:
Table 4-6. Interrupt Vector Table
Document Number: 001-66236 Rev. *A
1
2
3
4
5
6
7 – 10
11
12
13
14
15
16 – 47
0
1
2
3
4
5
6
7
8
32 interrupts. Multiple sources for each interrupt.
Configurable number of priority levels: from 3 to 8.
Dynamic reprioritization of interrupts.
Priority grouping. This allows selection of preempting and non
preempting interrupt levels.
Interrupt #
Exception
Number
“DSI Routing Interface Description”
Reset
NMI
Hard fault
MemManage
Bus fault
Usage fault
–
SVC
Debug monitor
–
PendSV
SYSTICK
IRQ
16
17
18
19
20
21
22
23
24
Exception Type
Cortex-M3 Exception #
–3 (highest)
–2
–1
Programmable
Programmable
Programmable
–
Programmable
Programmable
–
Programmable
Programmable
Programmable
Priority
PRELIMINARY
Low voltage detect (LVD)
Cache
Reserved
Sleep (Pwr Mgr)
PICU[0]
PICU[1]
PICU[2]
PICU[3]
PICU[4]
section on
Fixed Function
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C – 0x28
0x2C
0x30
0x34
0x38
0x3C
0x40 – 0x3FC
Exception Table
Address Offset
If the same priority level is assigned to two or more interrupts,
the interrupt with the lower vector number is executed first. Each
interrupt vector may choose from three interrupt sources: Fixed
Function, DMA, and UDB. The fixed function interrupts are direct
connections to the most common interrupt sources and provide
the lowest resource cost connection. The DMA interrupt sources
provide direct connections to the two DMA interrupt sources
provided per DMA channel. The third interrupt source for vectors
is from the UDB digital routing array. This allows any digital signal
available to the UDB array to be used as an interrupt source. All
interrupt sources may be routed to any interrupt vector using the
UDB interrupt source connections.
Support for tail-chaining, and late arrival, of interrupts. This
enables back-to-back interrupt processing without the
overhead of state saving and restoration between interrupts.
Processor state automatically saved on interrupt entry, and
restored on interrupt exit, with no instruction overhead.
PSoC
Starting value of R13 / MSP
Reset
Non maskable interrupt
All classes of fault, when the corresponding fault handler
cannot be activated because it is currently disabled or
masked
Memory management fault, for example, instruction fetch
from a nonexecutable region
Error response received from the bus system; caused by
an instruction prefetch abort or data access error
Typically caused by invalid instructions or trying to switch
to ARM mode
Reserved
System service call via SVC instruction
Debug monitor
Reserved
Deferred request for system service
System tick timer
Peripheral interrupt request #0 – #31
phub_termout0[0]
phub_termout0[1]
phub_termout0[2]
phub_termout0[3]
phub_termout0[4]
phub_termout0[5]
phub_termout0[6]
phub_termout0[7]
phub_termout0[8]
®
5: CY8C52 Family Datasheet
DMA
Function
Table
4-5.
udb_intr[0]
udb_intr[1]
udb_intr[2]
udb_intr[3]
udb_intr[4]
udb_intr[5]
udb_intr[6]
udb_intr[7]
udb_intr[8]
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UDB