CY8C5248LTI-030 Cypress Semiconductor Corp, CY8C5248LTI-030 Datasheet - Page 6

• Manufacturer Part Number: CY8C5248LTI-030
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5248LTI-030

• Lead Free Status / Rohs Status: Compliant

Figure 2-3
performance on a 2-layer board.
For information on circuit board layout issues for mixed signals, refer to the application note,
Layout Considerations for PSoC® 3 and PSoC
Document Number: 001-66236 Rev. *A
Note
5. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
The two pins labeled Vddd must be connected together.
The two pins labeled Vccd must be connected together, with capacitance added, as shown in
page 21. The trace between the two Vccd pins should be as short as possible.
The two pins labeled Vssd must be connected together.
(I2C0: SDA, SIO) P12[5]
(I2C0: SCL, SIO) P12[4]
(SWDCK, GPIO) P1[1]
(SWDIO, GPIO) P1[0]
(SWV, GPIO) P1[3]
and
Figure 2-4
(GPIO) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
(GPIO) P6[4]
(GPIO) P6[5]
(GPIO) P6[6]
(GPIO) P6[7]
(GPIO) P5[0]
(GPIO) P5[1]
(GPIO) P5[2]
(GPIO) P5[3]
(GPIO) P1[2]
(GPIO) P1[4]
(GPIO) P1[5]
Vboost
XRES
Vssb
Vssd
Vbat
Ind
show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog
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Lines show Vddio
to I/O supply
association
PRELIMINARY
Figure 2-2. 100-pin TQFP Part Pinout
5.
TQFP
PSoC
®
5: CY8C52 Family Datasheet
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AN57821 - Mixed Signal Circuit Board
Figure 2-3
Vddio0
P0[3] (GPIO, OpAmp0-/Extref0)
P0[2] (GPIO, OpAmp0+)
P0[1] (GPIO, OpAmp0out)
P0[0] (GPIO, OpAmp2out)
P4[1] (GPIO)
P4[0] (GPIO)
P12[3] (SIO)
P12[2] (SIO)
Vssd
Vdda
Vssa
Vcca
NC
NC
NC
NC
NC
NC
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
P3[7] (GPIO, OpAmp3out)
P3[6] (GPIO, OpAmp1out)
and
Power System
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