CY8C5248LTI-030 Cypress Semiconductor Corp, CY8C5248LTI-030 Datasheet - Page 9

• Manufacturer Part Number: CY8C5248LTI-030
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5248LTI-030

• Lead Free Status / Rohs Status: Compliant

4. CPU
4.1 ARM Cortex-M3 CPU
The CY8C52 family of devices has an ARM Cortex-M3 CPU core. The Cortex-M3 is a low power 32-bit three-stage pipelined Harvard
architecture CPU that delivers 1.25 DMIPS/MHz. It is intended for deeply embedded applications that require fast interrupt handling
features.
The Cortex-M3 CPU subsystem includes these features:
Document Number: 001-66236 Rev. *A
ARM Cortex-M3 CPU
Programmable nested vectored interrupt controller (NVIC),
tightly integrated with the CPU core
Full-featured debug and trace module, tightly integrated with
the CPU core
Up to 256 KB of flash memory, 2 KB of EEPROM, and 64 KB
of SRAM
SRAM
SRAM
32 KB
32 KB
Interrupt Inputs
SWD
Bus
Matrix
Bus
Matrix
Debug Block
AHB Spokes
Controller
Vectored
Interrupt
Nested
(NVIC)
(SWD)
GPIO
Flash Patch and
Breakpoint
AHB
I- Bus
(FPB)
Figure 4-1. ARM Cortex-M3 Block Diagram
AHB Bridge and Bus Matrix
PRELIMINARY
C- Bus
D- Bus
AHB
Digital
Prog.
Peripherals
PHUB
AHB
S-Bus
Cortex M3 Wrapper
Cortex M3 CPU Core
Analog
Prog.
4.1.1 Cortex-M3 Features
The Cortex-M3 CPU features include:
Cache controller
Peripheral HUB (PHUB)
DMA controller
4-GB address space. Predefined address regions for code,
data, and peripherals. Multiple buses for efficient and
simultaneous accesses of instructions, data, and peripherals.
PSoC
DMA
Bus
Matrix
®
Functions
Special
5: CY8C52 Family Datasheet
Cache
Instrumentation
Watchpoint and
Trace Module
Interface Unit
Trace (DWT)
Trace Port
(TPIU)
(ITM)
Data
256 KB
Flash
SWV
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