CY8C5248LTI-030 Cypress Semiconductor Corp, CY8C5248LTI-030 Datasheet - Page 43

• Manufacturer Part Number: CY8C5248LTI-030
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5248LTI-030

• Lead Free Status / Rohs Status: Compliant

8. Analog Subsystem
The analog programmable system creates application specific
combinations of both standard and advanced analog signal
processing blocks. These blocks are then interconnected to
each other and also to any pin on the device, providing a high
level of design flexibility and IP security. The features of the
analog subsystem are outlined here to provide an overview of
capabilities and architecture.
Document Number: 001-66236 Rev. *A
SDA
SCL
Flexible, configurable analog routing architecture provided by
analog globals, analog mux bus, and analog local buses
Condition
START
ADDRESS
1 - 7
GPIO
Port
A
N
A
L
O
G
R
O
U
T
N
G
I
R/W
8
Array
DSI
Figure 8-1. Analog Subsystem Block Diagram
Figure 7-22. I
ACK
9
PRELIMINARY
SAR
ADC
DAC
Distribution
Interface
Analog
Clock
CapSense Subsystem
2
CMP
1 - 7
Comparators
C Complete Transfer Timing
DATA
Registers
Config &
Status
Decimator
CMP
8
Successive approximation (SAR) ADC
One 8-bit DAC that provides either voltage or current output
Two comparators with optional connection to configurable LUT
outputs
CapSense subsystem to enable capacitive touch sensing
Precision reference for generating an accurate analog voltage
for internal analog blocks
PSoC
Reference
Precision
ACK
9
®
PHUB
5: CY8C52 Family Datasheet
1 - 7
A
N
A
L
O
G
R
O
U
T
N
G
I
DATA
CPU
GPIO
Port
8
ACK
9
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Condition
STOP