CY8C5248LTI-030 Cypress Semiconductor Corp, CY8C5248LTI-030 Datasheet - Page 39

• Manufacturer Part Number: CY8C5248LTI-030
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5248LTI-030

• Lead Free Status / Rohs Status: Compliant

Figure 7-13. Digital System Interconnect
Interrupt and DMA routing is very flexible in the CY8C52
programmable architecture. In addition to the numerous fixed
function peripherals that can generate interrupt requests, any
data signal in the UDB array routing can also be used to generate
a request. A single peripheral may generate multiple
independent interrupt requests simplifying system and firmware
design.
(Interrupt/DMA Multiplexer).
Figure 7-14. Interrupt and DMA Processing in the IDMUX
7.4.1 I/O Port Routing
There are a total of 20 DSI routes to a typical 8-bit I/O port, 16
for data and four for drive strength control.
When an I/O pin is connected to the routing, there are two
primary connections available, an input and an output. In
conjunction with drive strength control, this can implement a
bidirectional I/O pin. A data output signal has the option to be
Document Number: 001-66236 Rev. *A
Fixed Function DRQs
Counters
Timer
Fixed Function IRQs
Clocks
Global
Figure 7-14
CAN
IO Port
Pins
UDB Array
I2C
shows the structure of the IDMUX
Interrupt and DMA Processing in IDMUX
Digital System Routing I/F
Digital System Routing I/F
Del-Sig
UDB ARRAY
IRQs
DRQs
Controller
Interrupt
SC/CT
Blocks
Detect
Detect
Edge
Edge
Controller
DMA
DACs
0
1
0
2
1
2
3
IO Port
PRELIMINARY
Pins
Comparators
DMA termout (IRQs)
Clocks
Global
Controller
Controller
Interrupt
DMA
single synchronized (pipelined) and a data input signal has the
option to be double synchronized. The synchronization clock is
the system clock (see
are synchronized as this is required if the CPU interacts with the
signal or any signal derived from it. Asynchronous inputs have
rare uses. An example of this is a feed through of combinational
PLD logic from input pins to output pins.
Figure 7-15. I/O Pin Synchronization Routing
Figure 7-16. I/O Pin Output Connectivity
There are four more DSI connections to a given I/O port to
implement dynamic output enable control of pins. This
connectivity gives a range of options, from fully ganged 8-bits
controlled by one signal, to up to four individually controlled pins.
The output enable signal is useful for creating tristate
bidirectional pins and buses.
Figure 7-17. I/O Pin Output Enable Connectivity
4 IO Control Signal Connections from
DO
PIN 0
UDB Array Digital System Interface
DI
DO
PIN 0
PSoC
8 IO Data Output Connections from the
OE
UDB Array Digital System Interface
PIN1
PIN1
DO
OE
®
PIN2
5: CY8C52 Family Datasheet
PIN2
OE
DO
PIN3
Figure
OE
PIN3
DO
Port i
Port i
PIN4
OE
6-1). Normally all inputs from pins
PIN4
DO
PIN5
OE
PIN5
DO
PIN6
OE
PIN6
DO
PIN7
Page 39 of 95
OE
PIN7
DO