ATxmega32A4U Atmel Corporation, ATxmega32A4U Datasheet - Page 133

• Manufacturer Part Number: ATxmega32A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega32A4U

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.4
12.4.1
12.4.2
8331A–AVR–07/11
Interrupts
NMI – Non-Maskable Interrupts
Interrupt Response Time
The PMIC status register contains state information that ensures that the PMIC returns to the
correct interrupt level when the RETI (interrupt return) instruction is executed at the end of an
interrupt handler. Returning from an interrupt will return the PMIC to the state it had before enter-
ing the interrupt. The status register (SREG) is not saved automatically upon an interrupt
request. The RET (subroutine return) instruction cannot be used when returning from the inter-
rupt handler routine, as this will not return the PMIC to its correct state.
All interrupts and the reset vector each have a separate program vector address in the program
memory space. The lowest address in the program memory space is the reset vector. All inter-
rupts are assigned individual control bits for enabling and setting the interrupt level, and this is
set in the control registers for each peripheral that can generate interrupts. Details on each inter-
rupt are described in the peripheral where the interrupt is available.
All interrupts have an interrupt flag associated with it. When the interrupt condition is present,
the interrupt flag will be set, even if the corresponding interrupt is not enabled. For most inter-
rupts, the interrupt flag is automatically cleared when executing the interrupt vector. Writing a
logical one to the interrupt flag will also clear the flag. Some interrupt flags are not cleared when
executing the interrupt vector, and some are cleared automatically when an associated register
is accessed (read or written). This is described for each individual interrupt flag.
If an interrupt condition occurs while another, higher priority interrupt is executing or pending, the
interrupt flag will be set and remembered until the interrupt has priority. If an interrupt condition
occurs while the corresponding interrupt is not enabled, the interrupt flag will be set and remem-
bered until the interrupt is enabled or the flag is cleared by software. Similarly, if one or more
interrupt conditions occur while global interrupts are disabled, the corresponding interrupt flag
will be set and remembered until global interrupts are enabled. All pending interrupts are then
executed according to their order of priority.
Interrupts can be blocked when executing code from a locked section; e.g., when the boot lock
bits are programmed. This feature improves software security. Refer to memory programming
TBD for details on lock bit settings.
Interrupts are automatically disabled for up to four CPU clock cycles when the configuration
change protection register is written with the correct signature. Refer to
Protection” on page 12
Which interrupts represent NMI and which represent regular interrupts cannot be selected. Non-
maskable interrupts must be enabled before they can be used. Refer to the device datasheet for
NMI present on each device.
An NMI will be executed regardless of the setting of the I bit, and it will never change the I bit. No
other interrupts can interrupt a NMI handler. If more than one NMI is requested at the same time,
priority is static according to the interrupt vector address, where the lowest address has highest
priority.
The interrupt response time for all the enabled interrupts is three CPU clock cycles, minimum;
one cycle to finish the ongoing instruction and two cycles to store the program counter to the
stack. After the program counter is pushed on the stack, the program vector for the interrupt is
executed. The jump to the interrupt handler takes three clock cycles.
for more details.
Atmel AVR XMEGA AU
”Configuration Change
133