ATxmega32A4U Atmel Corporation, ATxmega32A4U Datasheet - Page 64

• Manufacturer Part Number: ATxmega32A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega32A4U

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8331A–AVR–07/11
Table 5-9.
Table 5-10.
Table 5-11.
Notes:
TRGSRC Offset Value
TRIGSRC Base Value
TRGSRC offset value
1. For DAC only, channel 0 and 1 exists and can be used as triggers.
2. Channel 4 equals ADC channel 0 to 3 ORed together.
+0x00
+0x01
+0x02
+0x00
+0x01
+0x02
+0x03
+0x04
0xAA
0xAB
0xAE
0x6A
0x6B
0x6E
0x8A
0x8B
0x8E
0xA0
0xA6
0x60
0x66
0x80
0x86
DMA trigger source base values for all modules and peripherals. (Continued)
DMA trigger source offset values for event system triggers.
DMA trigger source offset values for DAC and ADC triggers.
Group Configuration
Group Configuration
Group Configuration
USARTD0
USARTD1
USARTE0
USARTE1
USARTF0
USARTF1
CH2
CH4
TCD0
TCD1
TCE0
TCE1
TCF0
TCF1
SPID
SPIE
SPIF
CH0
CH1
CH2
CH0
CH1
CH3
(1)
(2)
Description
Timer/counter D0 DMA triggers base value
Timer/counter D1 triggers base value
SPI D DMA triggers value
USART D0 DMA triggers base value
USART D1 DMA triggers base value
Timer/counter E0 DMA triggers base value
Timer/counter E1 triggers base value
SPI E DMA triggers value
USART E0 DMA triggers base value
USART E1 DMA triggers base value
Timer/counter F0 DMA triggers base value
Timer/counter F1 triggers base value
SPI F DMA trigger value
USART F0 DMA triggers base value
USART F1 DMA triggers base value
Description
Event channel 0
Event channel 1
Event channel 2
Description
ADC/DAC channel 0
ADC/DAC channel 1
ADC channel 2
ADC channel 3
ADC channel 0, 1, 2, 3
Atmel AVR XMEGA AU
64